PGOOD

S5

TPS51116 PWP

VLDOIN

VTT

UDG-12044

VTTGND

GND

MODE

1

2

3

5

6

5VIN

VDDQ

VIN

0.033 ?F

VTTREF

COMP

VDDQSNS

8

9

7

20

19

PGND

DRVH

LL

18

17

16

DRVL

VBST

15

14

S3

V5IN

PGOOD

13

12

11

S5

CS

4

VTTSNS

1 kW

VDDQSET

10

TPS51116-EP

www.ti.com

SLUSB52A – OCTOBER 2012 – REVISED NOVEMBER 2012

Figure 2. Application Circuit When VTT Is Not Required

Controling Outputs Using the S3 and S5 Pins

In the DDR/DDR2/DDR3/LPDDR3 memory applications, it is important to keep VDDQ always higher than

VTT/VTTREF including both start-up and shutdown. TPS51116 provides this management by simply connecting

both the S3 and S5 pins to the sleep-mode signals such as SLP_S3 and SLP_S5 in the notebook PC system. All

of VDDQ, VTTREF and VTT are turned on at S0 state (S3 = S5 = high). In S3 state (S3 = low, S5 = high), VDDQ

and VTTREF voltages are kept on while VTT is turned off and left at high impedance (high-Z) state. The VTT

output is floated and does not sink or source current in this state. In S4/S5 states (S3 = S5 = low), all of the three

outputs are disabled. Outputs are discharged to ground according to the discharge mode selected by MODE pin

(see VDDQ and VTT Discharge Control section). Each state code represents as follow; S0 = full ON, S3 =

suspend to RAM (STR), S4 = suspend to disk (STD), S5 = soft OFF. (See Table 2)

Table 2. Sleep Mode Control Using the S3 and S5 Pins

STATE

S3

S5

VDDQ

VTTREF

VTT

S0

HI

HI

ON

ON

ON

S3

LO

HI

ON

ON

OFF (High-Z)

S4/S5

LO

LO

OFF (Discharge)

Off (Discharge)

OFF (Discharge)

Soft-Start and Powergood

The soft start function of the SMPS is achieved by ramping up reference voltage and two-stage current clamp. At

the starting point, the reference voltage is set to 650 mV (87% of its target value) and the overcurrent threshold

is set half of the nominal value. When UVP comparator detects VDDQ become greater than 80% of the target,

the reference voltage is raised toward 750 mV using internal 4-bit DAC. This takes approximately 85

μs. The

overcurrent threshold is released to nominal value at the end of this period. The powergood signal waits another

45

μs after the reference voltage reaches 750 mV and the VDDQ voltage becomes good (above 95% of the

target voltage), then turns off powergood open-drain MOSFET.

The soft-start function of the VTT LDO is achieved by current clamp. The current limit threshold is also changed

in two stages using an internal powergood signal dedicated for LDO. During VTT is below the powergood

threshold, the current limit level is cut into 60% (2.2 A).This allows the output capacitors to be charged with low

and constant current that gives linear ramp up of the output. When the output comes up to the good state, the

overcurrent limit level is released to normal value (3.8 A). TPS51116 has an independent counter for each

output, but the PGOOD signal indicates only the status of VDDQ and does not indicate VTT powergood

externally. See Figure 3.

Copyright © 2012, Texas Instruments Incorporated

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