3.5.4 LVCMOS Output Terminations

LVCMOS outputs are typically dc-coupled, as shown in the figure below.

3.3V , 2.5V , 1.8 V

LVCMOS

50

Rs

50

Rs

DC Coupled LVCMOS

OUTx

OUTxb

Figure 3.6. LVCMOS Output Terminations

3.5.5 LVCMOS Output Impedance and Drive Strength Selection

Each LVCMOS driver has a configurable output impedance. It is highly recommended that the minimum output impedance (strongest

drive setting) is selected and a suitable series resistor (Rs) is chosen to match the trace impedance.

Table 3.2. Nominal Output Impedance vs. OUTx_CMOS_DRV (register)

VDDO

CMOS_DRIVE_Selection

OUTx_CMOS_DRV=1

OUTx_CMOS_DRV=2

OUTx_CMOS_DRV=3

3.3 V

38 Ω

30 Ω

22 Ω

2.5 V

43 Ω

35 Ω

24 Ω

1.8 V

—

46 Ω

31 Ω

Note: Refer to the Si5340/41 Family Reference Manual for more information on register settings.

3.5.6 LVCMOS Output Signal Swing

VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers.

3.5.7 LVCMOS Output Polarity

When a driver is configured as an LVCMOS output it generates a clock signal on both pins (OUTx and OUTxb). By default the clock on

the OUTxb pin is generated with complementary polarity with the clock on the OUTx pin. The LVCMOS OUTx and OUTxb outputs can

also be generated in phase.

3.5.8 Output Enable/Disable

The OEb pin provides a convenient method of disabling or enabling the output drivers. When the OEb pin is held high all outputs will be

disabled. When held low, the outputs will be enabled. Outputs in the enabled state can be individually disabled through register control.

3.5.9 Output Driver State When Disabled

The disabled state of an output driver is configurable as: disable low or disable high.

Si5341/40 Rev D Data Sheet

Functional Description

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