Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Note:

1. Voltage swing is specified as single-ended mVpp.

Vpp_se

Vpp_se

Vpp_diff = 2*Vpp_se

Vcm

Vcm

2. Imposed for jitter performance.

3. Pulsed CMOS mode is intended primarily for single-ended LVCMOS input clocks < 1 MHz, which must be dc-coupled because

they have a duty cycle significantly less than 50%. A typical application example is a low frequency video frame sync pulse. Since

DC-coupled Pulsed LVCMOS in the Family Reference Manual. Otherwise, for standard LVCMOS input clocks, use the Standard

AC-Coupled, Single-ended input mode.

4. DC-coupled CMOS Input Buffer selection is not supported in ClockBuilder Pro for new designs. For single-ended LVCMOS inputs

to IN0,1,2 it is required to ac-couple into the differential input buffer.

Table 5.4. Control Input Pin Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Si5341 Control Input Pins (I2C_SEL, IN_SEL[1:0], RSTb, OEb, SYNCb, A1, SCLK, A0/CSb, FINC, FDEC, SDA/SDIO)

Input Voltage

—

—

V

—

—

V

Input Capacitance

—

2

—

pF

Input Resistance

—

20

—

kW

Minimum Pulse Width

RSTb, SYNCb, FINC, and

FDEC

100

—

—

ns

Frequency Update Rate

FINC and FDEC

—

—

1

MHz

Si5340 Control Input Pins (I2C_SEL, IN_SEL[1:0], RSTb, OEb, A1, SCLK, A0/CSb, SDA/SDIO)

Input Voltage

—

—

V

—

—

V

Input Capacitance

—

2

—

pF

Input Resistance

—

20

—

kW

Minimum Pulse Width

RSTb only

100

—

—

ns

Note:

details on register settings.

Si5341/40 Rev D Data Sheet

Electrical Specifications

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