SI5341_16 datasheet(23/53 Pages) SILABS

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Table 5.5. Differential Clock Output Specifications

(VDD=1.8 V ± 5%, VDDA=3.3V ± 5%, VDDO=1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 5%, TA= -40 to 85°C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Output Frequency

fOUT

MultiSynth not used

0.0001

—

720

MHz

733.33

—

800.00

825

—

1028

MultiSynth used

0.0001

—

720

MHz

Duty Cycle

fOUT < 400 MHz

—

400 MHz < fOUT < 1028 MHz

—

Output-Output Skew

Using Same MultiSynth

TSKS

Outputs on same MultiSynth

(Measured at 712.5 MHz)

—

Output-Output Skew

Between MultiSynths

TSKD

Outputs from different

MultiSynths

(Measured at 712.5 MHz)

—

OUT-OUTb Skew

TSK_OUT

Measured from the positive

to negative output pins

—

Output Voltage Swing1

VOUT

LVDS

350

430

510

mVpp_se

LVPECL

640

750

900

Common Mode Voltage1, 2

VCM

VDDO = 3.3 V

LVDS

1.10

1.2

1.3

LVPECL

1.90

2.0

2.1

VDDO = 2.5 V

LVPECL

LVDS

1.1

1.2

1.3

VDDO = 1.8 V

Sub-LVDS

0.8

0.9

1.0

Rise and Fall Times

(20% to 80%)

tR/tF

—

100

150

Differential Output Impedance

—

100

—

Power Supply Noise Rejection2

PSRR

10 kHz sinusoidal noise

—

–101

—

dBc

100 kHz sinusoidal noise

—

–96

—

500 kHz sinusoidal noise

—

–99

—

1 MHz sinusoidal noise

—

–97

—

Output-Output Crosstalk3

XTALK

Si5341

—

–72

—

dBc

Si5340

—

–88

—

dBc

Si5341/40 Rev D Data Sheet

Electrical Specifications

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