SI5341_16 datasheet(17/53 Pages) SILABS

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4.2 High-Level Register Map

Table 4.1. High-Level Register Map

16-Bit Address

Content

8-bit Page Address

8-bit Register Address Range

Revision IDs

Set Page Address

02-0A

Device IDs

0B-15

Alarm Status

17-1B

INTR Masks

Reset controls

2C-E1

Alarm Configuration

E2-E4

NVM Controls

Device Ready Status

Set Page Address

08-3A

Output Driver Controls

41-42

Output Driver Disable Masks

Device Ready Status

Set Page Address

02-05

XTAL Frequency Adjust

08-2F

Input Divider (P) Settings

Input Divider (P) Update Bits

35-3D

PLL Feedback Divider (M) Settings

PLL Feedback Divider (M) Update Bit

47-6A

Output Divider (R) Settings

6B-72

User Scratch Pad Memory

Device Ready Status

Set Page Address

02-37

MultiSynth Divider (N0-N4) Settings

MultiSynth Divider (N0) Update Bit

MultiSynth Divider (N1) Update Bit

MultiSynth Divider (N2) Update Bit

MultiSynth Divider (N3) Update Bit

MultiSynth Divider (N4) Update Bit

39-58

FINC/FDEC Settings N0-N4

59-62

Output Delay (Dt) Settings

63-94

Frequency Readback N0-N4

Device Ready Status

Si5341/40 Rev D Data Sheet

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