Table 5.2. DC Characteristics

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Core Supply Current1, 2

Si5340/41

—

115

230

mA

Si5340/41

—

120

130

mA

Output Buffer Supply Current

LVPECL Output3

@ 156.25 MHz

—

22

26

mA

LVDS Output3

@ 156.25 MHz

—

15

18

mA

3.3 V LVCMOS4 output

@ 156.25 MHz

—

22

30

mA

2.5 V LVCMOS4 output

@ 156.25 MHz

—

18

23

mA

1.8 V LVCMOS4 output

@ 156.25 MHz

—

12

16

mA

Total Power Dissipation1, 5

Si5341

—

880

1150

mW

Si5340

—

680

875

mW

Note:

1. Si5341 test configuration: 7 x 2.5 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors.

2. Si5340 test configuration: 4 x 2.5 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors.

3. Differential outputs terminated into an ac-coupled 100 Ω load.

4. LVCMOS outputs measured into a 6-inch 50 W PCB trace with 5 pF load. The LVCMOS outputs were set to

OUTx_CMOS_DRV=3, which is the strongest driver setting. Refer to the Si5341/40 Family Reference Manual for more details on

register settings.

50

50

100

OUT

OUTb

Differential Output Test Configuration

0. 1 uF

0. 1 uF

50

OUTa

5 pF

LVCMOS Output Test Configuration

6 inch

OUTb

5. Detailed power consumption for any configuration can be estimated using ClockBuilderPro when an evaluation board (EVB) is not

available. All EVBs support detailed current measurements for any configuration.

Si5341/40 Rev D Data Sheet

Electrical Specifications

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