AP0100CS datasheet(5/73 Pages) ONSEMI

5 / 73 page

AP0100CS/D Rev. 6, Pub. 1/16 EN

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

System Interfaces

Figure 2:

Typical Parallel Configuration

Notes:

1. This typical configuration shows only one scenario out of multiple possible variations for this

device.

2. ON Semiconductor recommends a 1.5kresistor value for the two-wire serial interface RPULL-UP;

however, greater values may be used for slower transmission speed.

3. RESET_BAR has an internal pull-up resistor and can be left floating if not used.

4. The decoupling capacitors for the regulator input and output should have a value of 1.0uF. The

capacitors should be ceramic and need to have X5R or X7R dielectric.

5. TRST_BAR connects to GND for normal operation.

6. ON Semiconductor recommends that 0.1F and 1F decoupling capacitors for each power supply

are mounted as close as possible to the pin. Actual values and numbers may vary depending on lay-

out and design consideration

VDDIO_OTPM

LDO_OP4

VDD_REG4

VDDIO_S6

VDDIO _S

VDDIO _H

Sensor IO

power

Host IO

power

M_SCLK

M_SDATA

EXTCLK_OUT

RESET_BAR_OUT

FV _IN

LV_IN

PIXCLK _IN

DIN [11:0]

TRIGGER_OUT

1. 8V

( R egulator

IP)

1 . 2 V ( R egulator OP)

P ower up C ore, P LL.

and DAC digital

GND_REG

FV_OUT

LV_OUT

PIXCLK_OUT

DOUT[15:0]

SCLK

SDATA

SADDR

SPI_CS_BAR

SPI_CLK

SPI_SDO

SPI_SDI

TRST_BAR5

OTPM

power

VDDIO_H

GND

GPIO_1

GPIO_2

GPIO_3

GPIO_4

GPIO_5

EXTCLK

XTAL

VDDIO_DAC

DAC_POS

DAC_NEG

DAC_REF

DAC

analog

power

FRAME_SYNC

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