AP0100CS datasheet(15/73 Pages) ONSEMI

15 / 73 page

AP0100CS/D Rev. 6, Pub. 1/16 EN

©Semiconductor Components Industries, LLC,2016.

AP0100CS HDR: Image Signal Processor (ISP)

On-Chip Regulator

Hard Reset

The AP0100CS enters the reset state when the external RESET_BAR signal is asserted

LOW, as shown in Figure 7. All the output signals will be in High-Z state.

Figure 7:

Hard Reset Operation

Soft Reset

A soft reset sequence to the AP0100 CS can be activated by writing to a register through

the two-wire serial interface.

Hard Standby Mode

The AP0100CS can enter hard standby mode by using external STANDBY signal, as

shown in Figure 8.

Entering Standby Mode

1. Assert STANDBY signal HIGH.

Table 8:

Hard Reset

Symbol

Definition

Min

Typ

Max

Unit

RESET_BAR pulse width

–

EXTCLK

cycles

Active EXTCLK required after RESET_BAR asserted

–

Active EXTCLK required before RESET_BAR de-

asserted

–

First two-wire serial interface communication after

RESET is HIGH

100

–

EXTCLK

Reset

RESET_BAR

Mode

Internal Initialization Time

SDATA

Enter streaming mode

All Outputs

Data Active

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