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AP0100CS 数据表(PDF) 6 Page - ON Semiconductor |
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AP0100CS 数据表(HTML) 6 Page - ON Semiconductor |
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6 / 73 page  AP0100CS HDR: Image Signal Processor (ISP) System Interfaces AP0100CS/D Rev. 6, Pub. 1/16 EN 6 ©Semiconductor Components Industries, LLC,2016. Figure 3: Typical HiSPi Configuration HiSPi and Parallel Connection When using the HiSPi interface, the user should connect the parallel interface to VDDIO_S. When using the parallel interface, the HiSPi interface and power supply (VDD_PHY) can be left floating. VDDIO_OTPM LDO_OP4 VDD_REG4 VDDIO_S6 VDDIO _S VDDIO _H Sensor IO power Host IO power M_SCLK M_SDATA EXTCLK_OUT RESET_BAR_OUT FV _IN LV_IN PIXCLK _IN DIN [11:0] TRIGGER_OUT 1. 8V ( R egulator IP) GND_REG FV_OUT LV_OUT PIXCLK_OUT DOUT[15:0] SCLK SDATA SADDR SPI_CS_BAR SPI_CLK SPI_SDO SPI_SDI TRST_BAR5 OTPM power VDDIO_H GND GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 EXTCLK XTAL VDDIO_DAC DAC_POS DAC_NEG DAC_REF CLK_N CLK_P DATA0_N DATA0_P DATA1_N DATA1_P 1 . 2 V ( R egulator OP) P ower up C ore, P LL. and DAC digital DAC analog power HiSPi voltage VDDIO_PHY Sensor IO power FRAME_SYNC |
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