AS4C2M32SA-7TCN datasheet(16/54 Pages) ALSC

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Figure 16. Termination of a Burst Read Operation (Burst Length＞4, CAS# Latency = 2, 3)

CLK

COMMAND

CAS# latency=2

tCK2, DQ

CAS# latency=3

tCK3, DQ

The burst ends after a delay equal to the CAS# latency

NOP

READ A

DOUT A0

DOUT A1

NOP

DOUT A1

DOUT A2

Burst

Stop

NOP

DOUT A3

DOUT A2

NOP

DOUT A3

NOP

Figure 17. Termination of a Burst Write Operation (Burst Length = X)

Don’t Care

CLK

COMMAND

NOP

WRITE A

DIN A0

NOP

DIN A1

NOP

DIN A2

Burst

Stop

NOP

Device Deselect command (CS# = "H")

The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE# and

Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar to the

No Operation command.

AutoRefresh command

(RAS# = "L", CAS# = "L", WE# = "H", CKE = "H", A0-A10 = Don't care)

The AutoRefresh command is used during normal operation of the SDRAM and is analogous to

CAS#-before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it must

be issued each time a refresh is required. The addressing is generated by the internal refresh controller.

This makes the address bits a "don't care" during an AutoRefresh command. The internal refresh

counter increments automatically on every auto refresh cycle to all of the rows. The refresh operation

must be performed 4096 times within 64ms. The time required to complete the auto refresh operation is

specified by tRC(min.). To provide the AutoRefresh command, all banks need to be in the idle state and

the device must not be in power down mode (CKE is high in the previous cycle). This command must

be followed by NOPs until the auto refresh operation is completed. The precharge time requirement,

tRP(min), must be met before successive auto refresh operations are performed.

SelfRefresh Entry command

(RAS# = "L", CAS# = "L", WE# = "H", CKE = "L", A0-A10 = Don't care)

The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh mode

for data retention and low power operation. Once the SelfRefresh command is registered, all the inputs

to the SDRAM become "don't care" with the exception of CKE, which must remain LOW. The refresh

addressing and timing is internally generated to reduce power consumption. The SDRAM may remain

in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited by restarting the external

clock and then asserting HIGH on CKE (SelfRefresh Exit command).

AS4C2M32SA-6TIN

AS4C2M32SA-6TCN

AS4C2M32SA-7TCN

Confidential

-16/54-

Rev.1.0 Sep. 2015

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