AS4C2M32SA-7TCN datasheet(21/54 Pages) ALSC

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Table 16. LVTTL Interface

Reference Level of Output Signals

1.4V / 1.4V

Output Load

Reference to the Under Output Load

Input Signal Levels (VIH /VIL)

2.4V / 0.4V

Transition Time (Rise and Fall) of Input Signals

1ns

Reference Level of Input Signals

1.4V

Output

1.2KΩ

30pF

3.3V

870Ω

Output

Z0=50Ω

50Ω

30pF

1.4V

Figure 18.1 LVTTL D.C. Test Load (A)

Figure 18.2 LVTTL A.C. Test Load (B)

7. Transition times are measured between VIH and VIL. Transition (rise and fall) of input signals are in a fixed

slope (1 ns).

8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels.

9. If clock rising time is longer than 1 ns, (tR / 2 -0.5) ns should be added to the parameter.

10. Assumed input rise and fall time tT (tR & tF ) = 1 ns

If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns should

be added to the parameter.

11. Power up Sequence

Power up must be performed in the following sequence.

1) Power must be applied to VDD and VDDQ (simultaneously) when CKE= “L”, DQM= “H” and all input

signals are held "NOP" state.

2) Start clock and maintain stable condition for minimum 200 µs, then bring CKE= “H” and, it is

recommended that DQM is held "HIGH" (VDD levels) to ensure DQ output is in high impedance.

3) All banks must be precharged.

4) Mode Register Set command must be asserted to initialize the Mode register.

5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the device.

* The Auto Refresh command can be issue before or after Mode Register Set command

AS4C2M32SA-6TIN

AS4C2M32SA-6TCN

AS4C2M32SA-7TCN

Confidential

-21/54-

Rev.1.0 Sep. 2015

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