ST92185B datasheet(82/178 Pages) STMICROELECTRONICS

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ST92185B - STANDARD TIMER (STIM)

STANDARD TIMER (Cont’d)

7.2.2.4 Standard Timer Output Modes

OUTPUT modes are selected using 2 bits of the

STC register: OUTMD1 and OUTMD2.

No Output Mode (OUTMD1 = “0”, OUTMD2 = “0”)

The output is disabled and the corresponding pin

is set high, in order to allow other alternate func-

tions to use the I/O pin.

Square Wave Output Mode (OUTMD1 = “0”,

OUTMD2 = “1”)

The Standard Timer toggles the state of the

STOUT pin on every End Of Count condition. With

INTCLK = 24MHz, this allows generation of a

square wave with a period ranging from 333ns to

5.59 seconds.

PWM Output Mode (OUTMD1 = “1”)

The value of the OUTMD2 bit is transferred to the

STOUT output pin at the End Of Count. This al-

lows the user to generate PWM signals, by modi-

fying the status of OUTMD2 between End of Count

events, based on software counters decremented

on the Standard Timer interrupt.

7.2.3 Interrupt Selection

The Standard Timer may generate an interrupt re-

quest at every End of Count.

Bit 2 of the STC register (INTS) selects the inter-

rupt source between the Standard Timer interrupt

and the external interrupt pin. Thus the Standard

Timer Interrupt uses the interrupt channel and

takes the priority and vector of the external inter-

rupt channel.

If INTS is set to “1”, the Standard Timer interrupt is

disabled; otherwise, an interrupt request is gener-

ated at every End of Count.

Note: When enabling or disabling the Standard

Timer Interrupt (writing INTS in the STC register)

an edge may be generated on the interrupt chan-

nel, causing an unwanted interrupt.

To avoid this spurious interrupt request, the INTS

bit should be accessed only when the interrupt log-

ic is disabled (i.e. after the DI instruction). It is also

necessary to clear any possible interrupt pending

requests on the corresponding external interrupt

channel before enabling it. A delay instruction (i.e.

a NOP instruction) must be inserted between the

reset of the interrupt pending bit and the INTS

write instruction.

7.2.4 Register Mapping

Depending on the ST9 device there may be up to 4

Standard Timers (refer to the block diagram in the

first section of the data sheet).

Each Standard Timer has 4 registers mapped into

Page 11 in Group F of the Register File

In the register description on the following page,

Note: The four standard timers are not implement-

ed on all ST9 devices. Refer to the block diagram

of the device for the number of timers.

STD Timer Register

STIM0

STH0

R240 (F0h)

STL0

R241 (F1h)

STP0

R242 (F2h)

STC0

R243 (F3h)

STIM1

STH1

R244 (F4h)

STL1

R245 (F5h)

STP1

R246 (F6h)

STC1

R247 (F7h)

STIM2

STH2

R248 (F8h)

STL2

R249 (F9h)

STP2

R250 (FAh)

STC2

R251 (FBh)

STIM3

STH3

R252 (FCh)

STL3

R253 (FDh)

STP3

R254 (FEh)

STC3

R255 (FFh)

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