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ST92185B 数据表(PDF) 87 Page - STMicroelectronics |
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ST92185B 数据表(HTML) 87 Page - STMicroelectronics |
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87 / 178 page  87/178 ST92185B - DISPLAY STORAGE RAM INTERFACE TDSRAM (Cont’d) 7.3.4 Register Description RAM INTERFACE CONFIGURATION REGIS- TER (CONFIG ) R252 - Read/Write Register Page: 38 Reset Value: 0000 0010 (02h) Bit 7:2 = Reserved, keep in reset state. Bit 1 = DON: Display ON/OFF. 0: No display reading allowed (display slot com- pletely used for CPU access). 1: Display reading enabled during the respective access slot. Note: DON can be changed only when the TRI is off (GEN = 0). < Bit 0 = GEN: RAM Interface General Enable. 0: TRI off. Display reading and CPU accesses are not allowed. When GEN=0, the Automatic Wait Cycle insertion, while trying to access the TDSRAM, is disabled. 1: TRI on. 70 0 0 0 0 0 0 DON GEN |
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