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ST72774 数据表(PDF) 71 Page - STMicroelectronics

部件名 ST72774
功能描述  8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C
PDF  144 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST72774 数据表(HTML) 71 Page - STMicroelectronics

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SYNC PROCESSOR (SYNC) (Cont’d)
LATCH REGISTER (LATR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = CSYN
Detection of pulses on CSYNCI
Set on falling edge of CSYNCI
Cleared by software (by writing zero).
Bit 6 = HSYN
Detection of pulses on HSYNCI
Set on falling edge of HSYNCI1 or HSYNCI2
Cleared by software (by writing zero).
Bit 5 = VSYN
Detection of pulses on VSYNCI
Set on falling edge of VSYNCI1 or VSYNCI2
Cleared by software (by writing zero).
Bit 4 = HFLY
Detection of pulses on HFBACK
Set on falling edge of HFBACK input
Cleared by software (by writing zero).
Bit 3 = VFLY
Detection of pulses on VFBACK
Set on falling edge of VFBACK input
Cleared by software (by writing zero).
Bit 2 = UPLAT
Detection of the maximum value of
5-bit up/down counter.
Set when the 5 bit up/down counter reaches its
maximum value (1Fh or Threshold)
Cleared by software (by writing zero).
Bit 1 = DWNLAT
Detection of minimum value of 5-
bit up/down counter.
Set when the 5 bit up/down counter reaches its
minimum value (00 or Threshold)
Cleared by software (by writing zero).
Note: DWNLAT and UPLAT may be used for HSYNCI po-
larity detection and Composite Sync detection as
follows:
Bit 0 = 2FHLAT
equalization pulses latch.
This bit may be used to detect pre/
postequalization pulses or a too high horizontal
frequency.
Set by hardware when Pre/Post equalization
pulses are detected.
Must be reset by software.
It is valid when the sync generator and Horizontal
analyzer are disabled (HVGEN = 0, HACQ = 0)
70
CSYN HSYN VSYN HFLY VFLY UPLAT DWNLAT 2FHLAT
UPLAT
DWNLAT
HSYNCI Characteristics
0
0
No Info
0
1
Positive Polarity
1
0
Negative Polarity
1
1
Composite Sync



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