ST72774 datasheet(35/144 Pages) STMICROELECTRONICS

35 / 144 page

ST72774/ST727754/ST72734

35/144

I/O PORTS (Cont’d)

4.1.6 Port D

The Port D I/O pins are normally used for the input

and output of video synchronization signals of the

Sync Processor, but are set to I/O Input with pull-

up upon reset. The I/O mode can be set

individually for each port bit to Input with pull-up

and output push-pull through the Port D DDR.

The configuration to support the Sync Processor

requires that the SYNOP (bit7) and CLMPEN (bit6)

of the ENR (Enable Register of SYNC) is reset.

SYNOP enables port D bits 0,1 and CLMPEN

enables Port D bit 6 to the sync outputs.

Port D, bit 4:3 are the alternate inputs ITA, ITB, (for

the interrupt falling edge detector).

When a falling edge occurs on these inputs, an

interrupt will be generated depending on the status

of the INTX (ITAITE & ITBITE) bits in the MISCR

Port D, bit 6 is switched to the alternate

(CLAMPOUT) by resetting the CLMPEN bit of the

ENR Register inside SYNC block.

If the SYNC function is selected, Port D bit 5 and 3

MUST be set as input to enable the HFBACK or

VFBACK timing inputs.

Note: As these inputs are switched from normal

I/O functionality, the video synchronization signals

may also be monitored directly through the Port D

Data Register for such tasks as checking for the

presence of video signals or checking the polarity of

Horizontal and Vertical synchronization signals

(when the Sync Inputs are switched directly to the

outputs using the multiplexers of the Sync Proces-

sor).

Table 11. Port D Description

PORT D

I / O

Alternate Function

Input*

Output

Signal

Condition

PD0

With pull-up

Push-pull

VSYNCO

(push pull output)

SYNOP=0

(ENR [SYNC])

PD1

With pull-up

Push-pull

HSYNCO

(push pull output)

SYNOP=0

(ENR [SYNC])

PD2

With pull-up

Push-pull

CSYNCI (input with TTL Schmitt

trigger & pull-up)

PD3

With pull-up

Push-pull

ITA (input with CMOS Schmitt

trigger & pull-up)

VFBACK (input with TTL Schmitt

trigger & pull-up)

PD4

With pull-up

Push-pull

ITB (input with CMOS Schmitt

trigger & pull-up)

PD5

With pull-up

Push-pull

HFBACK (input with TTL Schmitt

trigger & pull-up)

PD6

With pull-up

Push-pull

CLAMPOUT

(push pull output)

CLMPEN=0

(ENR [SYNC])

* Reset state

ST72774 数据表(PDF) 35 Page - STMicroelectronics

ST72774 数据表(HTML) 35 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

ST72774 数据表(PDF) 35 Page - STMicroelectronics

ST72774 数据表(HTML) 35 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载