ST72774 datasheet(75/144 Pages) STMICROELECTRONICS

75 / 144 page

ST72774/ST727754/ST72734

75/144

4.5 TIMING MEASUREMENT UNIT (TMU)

4.5.1 Introduction

The timing measurement unit (TMU) allows the

analysis of the current video timing characteristics

in order to control display position and size.

It consists of measuring the timing between the

horizontal or vertical sync output signals and the

active video signal input (AV).

4.5.2 Main Features

Horizontal or vertical timing measurement

Oscillator clock fOSC (24 or 12 MHz) used for

horizontal measurement

Horizontal sync signal (HSYNCO or HFBACK)

and Vertical sync signal (VSYNCO or VFBACK)

used for all measurements

Measurements performed on positive signals

only

11-bit counter

Overflow detection

4.5.3 Functional Description

The Timing Measurement Unit is centered around

an 11-bit counter. Depending on the H_V bit of the

control register, the TMU measures the horizontal

or vertical video characteristics.

For horizontal analysis (refer to Figure 48):

– Obtain the minimum number of oscillator clock

cycles (H1) between the falling edge of the

horizontal sync signal (HSYNCO or HFBACK)

and the first rising edge of the active video in-

put (AV), for all lines, between 2 consecutive

vertical sync pulses.

– Obtain the minimum number of oscillator clock

cycles (H2) between the last falling edge of

the active video input (AV) and the rising edge

of the horizontal sync signal (HSYNCO or HF-

BACK) for all lines, between 2 consecutive

vertical sync pulses.

Note: Horizontal measurement is inhibited during the high

level of VSYNCO or VFLYBACK.

For vertical analysis (refer to Figure 49):

– Obtain the minimum number of horizontal

sync pulses (V1) between the falling edge of

the vertical sync signal (VSYNCO or VF-

BACK) and the first rising edge of the active

video input, during 2 consecutive frames.

Figure 47. TMU Block Diagram

ST7 INTERNAL BUS

TMUT1CR

TMUT2CR

TMUCSR

11 bit COUNTER

T1[7:0]

T2[7:0]

T2[9] T2[8]

T1[9]

T1[8]

START

H_V

CONTROL

Clock

Start

Stop

HSYNCO or HFBACK (1)

VSYNCO or VFBACK (1)

fOSC

T2[10]

T1[10]

COMPARATOR

SUP

(FROM SYNC PROCESSOR)

Note 1: Selection between Sync outputs or Flyback inputs is made in MISCR register (bit 6: FLY_SYN)

ST72774 数据表(PDF) 75 Page - STMicroelectronics

ST72774 数据表(HTML) 75 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载