ST72774 datasheet(98/144 Pages) STMICROELECTRONICS

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ST72774/ST727754/ST72734

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DDC INTERFACE (Cont’d)

4.8.4 I2C BUS Protocol

A standard I2C communication is normally based

on four parts: START condition, device slave

address transmission, data transfer and STOP

condition. They are described brielfly in the

following section and illustrated in Figure 58 (for

more details, refer to the I2C bus specification).

4.8.4.1 START condition

When the bus is free (both SCL and SDA lines are

high

level),

master

can

initiate

communication by sending a START signal. This

signal is defined as a high-to-low transition of SDA

while SCL is stable high. The bus is considered to

be busy after a START condition.

This

START

condition

must

precede

any

command for data transfer.

4.8.4.2 Slave Address Transmission

The first byte following a START condition is the

slave address transmitted by the master. This

address is 7-bit long followed by an 8th bit (Least

significant bit: LSB) which is the data direction bit

(R/W bit).

– A “0” indicates a transmission (WRITE) from the

master to the slave.

– A “1” indicates a request for data (READ) from

the slave to the master.

If a slave device is present on the bus at the given

address, an Acknowledge will be generated on the

9th clock pulse.

4.8.4.3 Data Transfer

Once the slave address is acknowledged, the data

transfer can proceed in the direction given by the

R/W bit sent in the address.

Data is transferred with the most significant bit

(MSB) first. Data bits can be changed only when

SCL is low and must be held stable when SCL is

high.

One complete data byte transfer requires 9 clock

pulses: 8 bits + 1 acknowledge bit.

4.8.4.4 Acknowledge Bit (ACK / NACK)

Every byte put on the SDA line is 8-bit long

followed by an acknowledge bit.

This bit is used to indicate a successful data

transfer. The bus transmitter, either master or

slave, releases the SDA line during the 9th clock

period (after sending all 8 bits of data), then:

– To generate an Acknowledge (ACK) of the cur-

rent byte, the receiver pulls the SDA line low.

– To generate a No-Acknowledge (NACK) of the

current byte, the receiver releases the SDA line

(hence at a high level).

4.8.4.5 STOP Condition

A STOP condition is defined by a low-to-high

transition of SDA while SCL is stable high. It ends

the communication between the Interface and the

bus master.

Figure 58. I2C Signal Diagram

SDA

SCL

Start

Ack

A0h

Device Slave Address

00h

Data Address

Ack

Data1(B0h)

DataN(F0h) Ack STOP

WRITE DATA TO I2C DEVICE (Slave Address A0h)

SDA

SCL

Start

Ack

A1h

Device Slave Address

Data1(00h) Ack

Ack

Data2(B0h)

DataN(F0h) Nack STOP

READ DATA FROM I2C DEVICE (Slave Address A1h)

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