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ST72774 数据表(PDF) 56 Page - STMicroelectronics |
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ST72774 数据表(HTML) 56 Page - STMicroelectronics |
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56 / 144 page  ST72774/ST727754/ST72734 56/144 4.4 SYNC PROCESSOR (SYNC) 4.4.1 Introduction The Sync processor handles all the management tasks of the video synchronization signals, and is used with the timer and software to provide information and status on the video standard and timings. This block supports multiple video standards such as: Separate Sync, Composite Sync and (via an external extractor) Sync on Green. The internal clock in the Sync processor is 4 MHz. 4.4.2 Main Features s Input Processing – Presence of incoming signals (edge detection) – Read the HSYNCI / VSYNCI input signal levels – Measure the signal periods – Detect the sync polarities – Detect the composite sync and extract VSYNCO s Output Processing – Control the sync output polarities – Generate free-running frequencies – Generate a video blanking signal – Generate a clamping signal or a Moire signal s Analyzer Mode – Measure the number of scan lines per frame to simplify OSD vertical centering – Detect HSYNCI reaching too high a frequency – Detect pre/post equalization pulses – Measure the low level of HSYNCO or HFBACK s Corrector Mode – Inhibit Pre/Post equalization pulses – Program VSYNCO pulse width extension – Extend VSYNCO pulse widths during: post-equalization pulse detection only pre and post-equalization pulse detection Note: Some external pins are not available on all devices. Refer to the device pinout description. Figure 37. Sync Processor Block Diagram Sync Generator Sync Analyzer Sync Corrector Hardware Block VSYNC Generator 40 - 200 Hz Typical Pulse Width 20 - 256 µs HSYNC Generator 15 - 200 kHz Duty cycle range 3 - 40 % Latch 00 match Latch 1F match LCV0 Sync & Edge Detect Capture Register LD V Sync O Polarity V Sync Correction Polarity Detector Pull-Up Resistor (if existing) VSYNCI1 VSYNCO 1 0 HSYNCI2 CLAMPOUT HSYNCO ICAP1 TIMER HVGEN CSYNCI CLPINV 1 0 LCV1 Vsync* LCV1 SCI0 ICAP2 TIMER VSYNCI HSYNCI / CSYNCI PSCD HVGEN 1 0 SYNOP SYNOP H Sync O Polarity H Sync O Correction H-Inhibit ON/OFF Back Porch Clamp Generator Clamp Polarity Latch Pulse Detect Prescaler V S Y N C O 5-Bit Counter EN Up / Down CLK fINT Control Logic VR02071C CLMPEN 0 1 VFBACK 1 0 FBSEL FBSEL 00 Other BP1, BP0 HFBACK VFBACK Latch Pulse Detect Latch Pulse Detect VSYNCI2 1 0 HVSEL 1 0 HVSEL HSYNCI1 (Positive polarity) HFBACK Blanking Generator BLANKOUT BLKEN (see note) Note: CLK is fINT/2 in fast mode (see note in Clock System section) |
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