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ST72774 数据表(PDF) 103 Page - STMicroelectronics |
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ST72774 数据表(HTML) 103 Page - STMicroelectronics |
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103 / 144 page ![]() ST72774/ST727754/ST72734 103/144 Figure 63. DDC1/2B Operation Flowchart SDA Hi-Z Vsync Counter = 0 Start 2-sec Timer N Y SCL N Received valid Device Address? Y N Vsync Counter += 1 Counter = 128 or Timer expired ? Send Next Bit Relative Address (ALR) = 0 Wait for HWPE = 1 Vsync Counter = 0 Re-Start 2-sec Timer Y Y Y N N HWPE bit = 0 Vsync SCL CF0 = 0 Vsync N Y Y N Received valid Device Address? N Respond to Command Send Acknowledge Y Relative Address (ALR) = 0 CF2 = 0 ? and |
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