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STM32L475VC 数据表(PDF) 175 Page - STMicroelectronics |
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STM32L475VC 数据表(HTML) 175 Page - STMicroelectronics |
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175 / 193 page  DocID027692 Rev 2 175/193 STM32L475xx Electrical characteristics 181 Table 90. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) 1. CL = 30 pF. 2. Guaranteed by characterization results. Symbol Parameter Min Max Unit tw(NE) FMC_NE low time 3THCLK-0.5 3THCLK+2 ns tv(NOE_NE) FMC_NEx low to FMC_NOE low 2THCLK-0.5 2THCLK+0.5 tw(NOE) FMC_NOE low time THCLK+0.5 THCLK+1 th(NE_NOE) FMC_NOE high to FMC_NE high hold time 0 - tv(A_NE) FMC_NEx low to FMC_A valid - 3 tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 1 tw(NADV) FMC_NADV low time THCLK-0.5 THCLK+1 th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high 0 - th(A_NOE) Address hold time after FMC_NOE high THCLK-0.5 - th(BL_NOE) FMC_BL time after FMC_NOE high 0 - tv(BL_NE) FMC_NEx low to FMC_BL valid - 2 tsu(Data_NE) Data to FMC_NEx high setup time THCLK-2 - tsu(Data_NOE) Data to FMC_NOE high setup time THCLK-1 - th(Data_NE) Data hold time after FMC_NEx high 0 - th(Data_NOE) Data hold time after FMC_NOE high 0 - Table 91. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)(2) 1. CL = 30 pF. 2. Guaranteed by characterization results. Symbol Parameter Min Max Unit tw(NE) FMC_NE low time 8THCLK+2 8THCLK+4 ns tw(NOE) FMC_NWE low time 5THCLK-1 5THCLK+1.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5THCLK+1.5 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK+1 - |
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