USB3450

DS00002105A-page 16

5.3

RX Logic

This block receives serial data from the clock recovery circuits and processes it to be transferred to the Link on the DATA

bus. The processing involved includes NRZI decoding, bit unstuffing, and serial to parallel conversion. Upon valid asser-

tion of the proper RX control lines, the RX Logic block will provide bytes to the DATA bus as shown in the figures below.

The behavior of the receiver is described below.

The assertion of RESET will cause the USB3450 to deasserts RXACTIVE and RXVALID. When the RESET signal is

deasserted the Receive State Machine starts looking for a SYNC pattern on the USB. When a SYNC pattern is detected

the receiver will assert RXACTIVE. The length of the received Hi-Speed SYNC pattern varies and can be up to 32 bits

long or as short as 12 bits long when at the end of five hubs.

After valid serial data is received, the data is loaded into the RX Holding Register on the rising edge of CLKOUT and

RXVALID is asserted. The Link must clock the data off the DATA bus on the next rising edge of CLKOUT. In normal

mode (OPMODE = 00), then stuffed bits are stripped from the data stream. Each time 8 stuffed bits are accumulated

the USB3450 will negate RXVALID for one clock cycle, thus skipping a byte time.

When the EOP is detected the USB3450 will negate RXACTIVE and RXVALID. After the EOP has been stripped the

USB3450 will begin looking for the next packet.

The behavior of the USB3450 receiver is described below:

• RXACTIVE and RXREADY are sampled on the rising edge of CLKOUT.

• After a EOP is complete the receiver will begin looking for SYNC.

• The USB3450 asserts RXACTIVE when SYNC is detected.

• The USB3450 negates RXACTIVE when an EOP is detected and the elasticity buffer is empty.

• When RXACTIVE is asserted, RXVALID will be asserted if the RX Holding Register is full.

• RXVALID will be negated if the RX Holding Register was not loaded during the previous byte time. This will occur

if 8 stuffed bits have been accumulated.

• The Link must be ready to consume a data byte if RXACTIVE and RXVALID are asserted (RX Data state).

• Figure 5-5 shows the timing relationship between the received data (DP/DM), RXVALID, RXACTIVE, RXERROR

and DATA signals.

FIGURE 5-4:

RECEIVE TIMING FOR DATA WITH UNSTUFFED BITS

Note:

• Figure 5-5, Figure 5-6 and Figure 5-7 are timing examples of a HS/FS PHY when it is in HS mode. When a

HS/FS PHY is in FS Mode there are approximately 40 CLKOUT cycles every byte time. The Receive State

Machine assumes that the Link captures the data on the DATA bus if RXACTIVE and RXVALID are asserted. In

FS mode, RXVALID will only be asserted for one CLKOUT per byte time.

•In Figure 5-5, Figure 5-6 and Figure 5-7 the SYNC pattern on DP/DM is shown as one byte long. The SYNC pat-

tern received by a device can vary in length. These figures assume that all but the last 12 bits have been con-

sumed by the hubs between the device and the host controller.