DS00002105A-page 19

USB3450

5.4.3

BIAS GENERATOR

This block consists of an internal bandgap reference circuit used for generating the high speed driver currents and the

biasing of the analog circuits. This block requires an external 12K

, 1% tolerance, external reference resistor connected

from RBIAS to ground.

5.5

Crystal Oscillator and PLL

The USB3450 uses an internal crystal driver and PLL sub-system to provide a clean 480MHz reference clock that is

used by the PHY during both transmit and receive. The USB3450 requires a clean 24MHz crystal or clock as a frequency

reference. If the 24MHz reference is noisy or off frequency the PHY may not operate correctly.

The USB3450 can use either a crystal or an external clock oscillator for the 24MHz reference. The crystal is connected

to the XI and XO pins as shown in the application diagram, Figure 6-9. If a clock oscillator is used the clock should be

connected to the XI input and the XO pin left floating. When an external clock is used the XI pin is designed to be driven

with a 0 to 3.3 volt signal. When using an external clock the user needs to take care to ensure the external clock source

is clean enough to not degrade the high speed eye performance.

Once, the 480MHz PLL has locked to the correct frequency it will drive the CLKOUT pin with a 60MHz clock. The

USB3450 will start the clock within the time specified in Table 4-2.

FIGURE 5-8:

DP/DM TERMINATION VS. SIGNALING MODE

Signaling Mode

UTMI+ Interface Settings

Resistor Settings

General Settings

Tri-State Drivers

XXb

Xb

01b

Xb

0b

0b

0b

0b

0b

01b

0b

00b

1b

0b

0b

1b

1b

0b

Host Settings

Host Chirp

00b

0b

10b

1b0b

0b

1b1b1b

Host Hi-Speed

00b

0b

00b

1b

0b

0b

1b

1b

1b

Host Full Speed

X1b

1b

00b

1b0b

0b

1b1b0b

Host HS/FS Suspend

01b

1b

00b

1b

0b

0b

1b

1b

0b

Host HS/FS Resume

01b

1b

10b

1b

0b

0b

1b

1b

0b

Host low Speed

10b

1b

00b

1b

0b

0b

1b

1b

0b

Host LS Suspend

10b

1b

00b

1b

0b

0b

1b

1b

0b

Host LS Resume

10b

1b

10b

1b

0b

0b

1b

1b

0b

Host Test J/Test_K

00b

0b

10b

1b

0b

0b

1b

1b

1b

Peripheral Settings

Peripheral Chirp

00b

1b

10b

0b

1b

0b

0b

0b

0b

Peripheral HS

00b

0b

00b

0b

0b

0b

0b

0b

1b

Peripheral FS

01b

1b

00b

0b

1b

0b

0b

0b

0b

Peripheral HS/FS Suspend

01b

1b

00b

0b

1b

0b

0b

0b

0b

Peripheral HS/FS Resume

01b

1b

10b

0b

1b

0b

0b

0b

0b

Peripheral LS

10b

1b

00b

0b

0b

1b

0b

0b

0b

Peripheral LS Suspend

10b

1b

00b

0b

0b

1b

0b

0b

0b

Peripheral LS Resume

10b

1b

10b

0b

0b

1b

0b

0b

0b

Peripheral Test J/Test K

00b

0b

10b

0b

0b

0b

0b

0b

1b