数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

STGAP1AS 数据表(PDF) 63 Page - STMicroelectronics

部件名 STGAP1AS
功能描述  Automotive galvanically isolated advanced single gate driver
PDF  70 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STGAP1AS 数据表(HTML) 63 Page - STMicroelectronics

Back Button STGAP1AS Datasheet HTML 59Page - STMicroelectronics STGAP1AS Datasheet HTML 60Page - STMicroelectronics STGAP1AS Datasheet HTML 61Page - STMicroelectronics STGAP1AS Datasheet HTML 62Page - STMicroelectronics STGAP1AS Datasheet HTML 63Page - STMicroelectronics STGAP1AS Datasheet HTML 64Page - STMicroelectronics STGAP1AS Datasheet HTML 65Page - STMicroelectronics STGAP1AS Datasheet HTML 66Page - STMicroelectronics STGAP1AS Datasheet HTML 67Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 63 / 70 page
background image
DocID029344 Rev 2
63/70
STGAP1AS
Programming manual
70
A description of the STATUS3 register bits is provided in Table 53.
9.2.9
TEST1 register (isolated side)
The TEST1 register has the structure of Table 54.
Setting an one check bit of the register enables the respective check mode.
Table 53. STATUS3 register description
Name
Bit
Fault
Latched
Force
“safe state”
Note
DT_ERR
4
Deadtime error flag.
This bit is forced high when a violation of
internal DT is detected.
Always
No
See details in Section 7.2
on page 26
SPI_ERR
3
SPI communication error flag.
It is forced high when the SPI
communication fails cause:
– Wrong CRC check.
– Wrong number of CK rising edges.
– Attempt to execute a not-allowed
command.
Attempt to read, write or reset at a not-
available address.
Always
No
-
REGERRL
2
Register or communication error on low
voltage side.
It is forced high when: -
– Programming procedure is not correctly
performed.
– Isolated interface communication fails.
– An unexpected register value change
occurs in one of the remote registers.
It is latched at power-up/reset also.
Always
Yes
-
OVLOD
1
VDD overvoltage flag.
It is forced high when VDD is over
OVVDDoff threshold.
Always
Yes
-
UVLOD
0
VDD undervoltage flag.
It is forced high when VDD is below VDDon
threshold. It is latched at power-up/reset
also.
Always
Yes
-
Table 54. TEST1 register
-
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
GOFFCHK
GONCHK
DESCHK
SNSCHK
RCHK
Default/reset
x
x
x
0
0
0
0
0



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com