STGAP1AS datasheet(36/70 Pages) STMICROELECTRONICS

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Functional description

STGAP1AS

36/70

DocID029344 Rev 2

All flags in the StatusRegisters are released after a tdesCS time following the rise of the

SPI CS.



Forcing low the SD pin for at least trelease

All the flags are released at the rising edge of the SD. This mode is enabled at device’s

power-on, but it can be disabled by setting the SD_FLAG configuration bit low during

the configuration phase, and by doing this any possibility to clear a FLAG without direct

intervention of the MCU is prevented. Even if the SD_FLAG is set high, status registers

are not cleared after the rising edge of the SD if a configuration sequence is executed

(StartConfig, StopConfig). This is done to avoid clearing errors that may have been

generated during the configuration procedure.



Using HW reset

(see Section 7.3 on page 29)

In this case the device behaves as after power-up sequence.

In any case, if the failure condition is still present, the respective flag is not released.

Selected failures force the device in “safe state”; the device remains in this state until the

relative status flags are released. Refer to Table 49 on page 61, Table 51 on page 62 and

Table 53 on page 63

for details.

The possibility to clear status registers by setting the SD low allows operating the device

also without using the SPI interface. In order to avoid an unintended clear of fault conditions

it is recommended to disable this functionality by setting the SD_FLAG = '0'.

7.12

Asynchronous stop command

The ASC pin allows to turn-on the GON output acting directly on the isolated driver logic and

regardless of the status of the input pins IN+, IN- and SD. This pin is active high.

The status of this pin is mirrored in the ASC bit present in the STATUS2 register.

The power supply of the isolated section must be present (VH > VHon).

In case UVLO on VH is not enabled, ASC function works for VH values within the

recommended operating values.

This function works even if the VDD voltage is not available or is in UVLO condition.

The priority of such command is lower than that of DESAT and SENSE pins, so the ASC

command is ignored in case of a desaturation or overcurrent fault. After such events the

gate can be turned on again with a low-to-high transition of the ASC pin, or by clearing the

fault condition (see Section 7.11).

7.13

Watchdog and echo

The isolated side provides a watchdog function in order to identify when it is no more able to

communicate with the LV side. In this case the driver is automatically forced in “safe state”

and the REGERRR flag is set.

When the LV side is in the standby mode, turned off or in hardware reset condition, the

isolated side watchdog is still operative and the REGERRR flag is set.

The low voltage side provides a watchdog function in order to identify when it is no more

able to communicate with the isolated side. In this case the REGERRL flag is set and the

device is forced in “safe state”.

STGAP1AS 数据表(PDF) 36 Page - STMicroelectronics

STGAP1AS 数据表(HTML) 36 Page - STMicroelectronics

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