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WM8281ECS/R 数据表(PDF) 387 Page - Cirrus Logic |
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WM8281ECS/R 数据表(HTML) 387 Page - Cirrus Logic |
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387 / 392 page  WM8281 Rev 4.0 387 In each case, the SYSCLK (ASYNCCLK) frequency must be a valid ratio to the LRCLK frequency; the supported clocking rates are defined by the SYSCLK_FREQ (ASYNC_CLK_FREQ) and SAMPLE_RATE_n (ASYNC_SAMPLE_RATE_n) registers. The valid AIF clocking configurations are illustrated in Figure 95 to Figure 101 below. Note that, where MCLK1 is illustrated as the clock source, it is equally possible to select MCLK2 as the clock source. Similarly, in cases where FLL1 is illustrated, it is equally possible to select FLL2. AIFn (Master Mode) Oscillator WM8281 Processor AIFnBCLK AIFnLRCLK AIFnRXDAT AIFnTXDAT SYSCLK (or ASYNCCLK) SYSCLK_SRC (or ASYNCCLK_SRC) Figure 95 AIF Master Mode, using MCLK as Reference Oscillator WM8281 AIFn (Master Mode) Processor AIFnBCLK AIFnLRCLK AIFnRXDAT AIFnTXDAT FLL1_REFCLK_SRC FLL1 SYSCLK (or ASYNCCLK) SYSCLK_SRC (or ASYNCCLK_SRC) Figure 96 AIF Master Mode, using MCLK and FLL as Reference |
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