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WM8281ECS/R 数据表(PDF) 389 Page - Cirrus Logic |
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WM8281ECS/R 数据表(HTML) 389 Page - Cirrus Logic |
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389 / 392 page  WM8281 Rev 4.0 389 WM8281 AIFn (Slave Mode) AIFnBCLK AIFnLRCLK AIFnRXDAT AIFnTXDAT FLL1_REFCLK_SRC FLL1 Processor Synchronous Clock Generator SYSCLK (or ASYNCCLK) SYSCLK_SRC (or ASYNCCLK_SRC) Figure 100 AIF Slave Mode, using MCLK and FLL as Reference WM8281 AIFn (Slave Mode) AIFnBCLK AIFnLRCLK AIFnRXDAT AIFnTXDAT FLL1_REFCLK_SRC FLL1 Processor Synchronous Clock Generator SYSCLK (or ASYNCCLK) SYSCLK_SRC (or ASYNCCLK_SRC) AIFn (Slave Mode) AIFnBCLK AIFnLRCLK AIFnRXDAT AIFnTXDAT SLIMbus Interface SLIMCLK SLIMDAT Automatic Divider FRAMER_REF_GEAR Processor Processor Figure 101 AIF Slave Mode, using another Interface as Reference PCB LAYOUT CONSIDERATIONS Poor PCB layout will degrade the performance and be a contributory factor in EMI, ground bounce and resistive voltage losses. All external components should be placed as close to the WM8281 device as possible, with current loop areas kept as small as possible. |
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