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MB91F465KB 数据表(PDF) 60 Page - Cypress Semiconductor

部件名 MB91F465KB
功能描述  32-bit RISC, load/store architecture, five-stage pipeline
PDF  86 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

MB91F465KB 数据表(HTML) 60 Page - Cypress Semiconductor

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MB91460K Series
Document Number: 002-04602 Rev. *A
Page 60 of 86
86
14. Recommended Settings
14.1
PLL and Clockgear settings
Please note that for MB91F465Kx, the core base clock frequencies are valid in the 1.8V operation mode of the Main regulator and Flash.
Table 5: Recommended PLL divider and clockgear settings
PLL
Input (CLK)
[MHz]
Frequency Parameter
Clockgear Parameter
PLL
Output (X)
[MHz]
Core Base
Clock
[MHz]
Remarks
DIVM
DIVN
DIVG
MULG
MULG
4
2
25
16
24
200
100
[1]
1. This setting is not possible at MB91F465Kx
4
2
24
16
24
192
96
[1]
4
2
23
16
24
184
92
[1]
4
2
22
16
24
176
88
[1]
4
2
21
16
20
168
84
[1]
4
2
20
16
20
160
80
4
2
19
16
20
152
76
4
2
18
16
20
144
72
4
2
17
16
16
136
68
4
2
16
16
16
128
64
4
2
15
16
16
120
60
4
2
14
16
16
112
56
4
2
13
16
12
104
52
4
2
12
16
12
96
48
4
2
11
16
12
88
44
4
4
10
16
24
160
40
4
4
9
16
24
144
36
4
4
8
16
24
128
32
4
4
7
16
24
112
28
4
6
6
16
24
144
24
4
8
5
16
28
160
20
4
10
4
16
32
160
16
4
12
3
16
32
144
12



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