MB91F465KB datasheet(19/86 Pages) CYPRESS

19 / 86 page

MB91460K Series

Document Number: 002-04602 Rev. *A

Page 19 of 86

5.6

Mode Pins (MD_x)

These pins should be connected directly to the power supply or ground pins. To prevent the device from entering test mode

accidentally due to noise, minimize the lengths of the patterns between each mode pin and power supply pin or ground pin on

the printed circuit board as possible and connect them with low impedance.

5.7

Notes on Operating in PLL Clock Mode

If the oscillator is disconnected or the clock input stops when the PLL clock is selected, the microcontroller may continue to

operate at the free-running frequency of the self-oscillating circuit of the PLL. However, this self-running operation cannot

be guaranteed.

5.8

Pull-Up Control

The AC standard is not guaranteed in case a pull-up resistor is connected to the pin serving as an external bus pin.

5.9

Notes on PS Register

As the PS register is processed in advance by some instructions, when the debugger is being used, the exception handling may

result in execution breaking in an interrupt handling routine or the displayed values of the flags in the PS register being updated.

As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event,the operation before

and after the EIT always proceeds according to specification.

■ The following behavior may occur if any of the following occurs in the instruction immediately after a DIV0U/DIV0S

instruction:

(a) a user interrupt or NMI is accepted;

(b) single-step execution is performed;

1. D0 and D1 flags are updated in advance.

2. An EIT handling routine (user interrupt/NMI or emulator) is executed.

3. Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are updated to the

same values as those in 1.

■ The following behavior occurs when an ORCCR, STILM, MOV Ri,PS instruction is executed to enable a user

interrupt or NMI source while that interrupt is in the active state.

1. The PS register is updated in advance.

2. An EIT handling routine (user interrupt/NMI or emulator) is executed.

3. Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same value

as in 1.

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