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MB91F465KB 数据表(PDF) 81 Page - Cypress Semiconductor

部件名 MB91F465KB
功能描述  32-bit RISC, load/store architecture, five-stage pipeline
PDF  86 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

MB91F465KB 数据表(HTML) 81 Page - Cypress Semiconductor

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MB91460K Series
Document Number: 002-04602 Rev. *A
Page 81 of 86
86
15.6.5 Free-Run Timer Clock
(VDD5  3.0 V to 5.5 V, VSS5  AVSS5  0 V, TA  40°C to  105°C)
Note: tCLKP is the cycle time of the peripheral clock.
15.6.6 Trigger Input Timing
(VDD5 3.0 V to 5.5 V, VSS5 AVSS5 0 V, TA 40°C to  105°C)
Note: tCLKP is the cycle time of the peripheral clock.
Parameter
Symbol
Pin name
Condition
Value
Unit
Min
Max
Input pulse width
tTIWH
tTIWL
CKn
-
4tCLKP
-
ns
Parameter
Symbol
Pin name
Condition
Value
Unit
Min
Max
Input capture input trigger
tINP
ICUn
-
5tCLKP
-
ns
A/D converter trigger
tATGX
ATGX
-
5tCLKP
-
ns
tTIWH
tTIWL
CKn
ICUn,
ATGX
tATGX, tINP



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