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WM8214

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PP Rev 1.6 March 2004

9

Figure 3 Single-channel CDS Input Video Timing

Notes:

1.

The relationship between input video and sampling is controlled by VSMP and RSMP.

2.

When VSMP is high the input video signal is connected to the Video sampling capacitors.

3.

When RSMP is high the input video signal is connected to the Reset sampling capacitors.

4.

RSMP must not go high before the first falling edge of MCLK after VSMP goes low.

5.

It is required that the falling edge of VSMP should occur before the rising edge of MCLK.

6.

In 1-channel CDS mode it is not possible to have a equally spaced Video and Reset sample points with a 40MHz

MCLK.

7.

Non-CDS operation is also possible; RSMP is not required in this mode.

Test Conditions

°C, MCLK = 40MHz unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

MCLK period

25

ns

MCLK high period

11.3

12.5

ns

MCLK low period

11.3

12.5

ns

RSMP pulse high time

5

ns

VSMP pulse high time

5

ns

RSMP falling to VSMP rising time

0

ns

MCLK rising to VSMP rising time

3

ns

MCLK falling to VSMP falling time

5

ns

VSMP falling to MCLK rising time

1

ns

1

to RSMP rising time

1

ns

3-channel mode pixel rate

75

ns

2-channel mode pixel rate

50

ns

1-channel mode pixel rate

25

ns

Output propagation delay

10

ns

Notes:

1.

Parameters are measured at 50% of the rising/falling edge.