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WM8214

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PP Rev 1.6 March 2004

13

In situations where the input video signal does not have a stable reference level it may be necessary

to clamp only during those pixels which have a known state (e.g. the dummy, or “black” pixels at the

start or end of a line most image sensors). This is known as line-clamping and relies on the input

capacitor to hold the DC level between clamp intervals. In non-CDS mode (CDS=0) this can be done

directly by controlling the RSMP input pin to go high during the black pixels only.

Alternatively it is possible to use RSMP to identify the black pixels and enable the clamp at the same

time as the input is being sampled (i.e. when VSMP is high and RSMP is high).

This mode is

enabled by setting CLMPCTRL=1 and the operation is shown in Figure 7.

MCLK

VSMP

RSMP

RLC switch control,

"CLMP"

(RLCEN=1,CLMPCTRL=1)

RLC switch closed when RSMP=1 &&

VSMP=1 (during "black" pixels)

Video and reference sample

taken on fallling edge of VSMP

INPUT VIDEO

SIGNAL

unstable

reference level

dummy or

"black" pixel

video level

Figure 7 Reset Level Clamp Operation (CLMPCTRL=1), non-CDS mode only

When in LEGACY mode all timing, including the RLC switch timing, is derived from MCLK and

VSMP. MCLK operates at double the ADC conversion rate and VSMP determines the sample rate of

the device.

Reset Level Clamping in LEGACY mode is only possible in CDS mode and the time at which the

clamp switch is closed is concurrent with the reset sample period, RS, as shown in Figure 8. RLC

can be enabled on a pixel by pixel basis under control of the RSMP input pin. If RSMP is high when

VSMP is high and is sampled by MCLK then clamping will be enabled for that input sample at the

time determined by CDSREF[1:0]. If RSMP is low at this point then the RLC switch will not be closed

for that input sample.

If RLC is required on every pixel then the RSMP pin can be constantly held

high in LEGACY mode.

MCLK

VSMP

t

LVSMPSU

t

LVSMPH

Video Sample, "VS"

Reset Sample, "RS"

(CDS=1, CDSREF=00 )

Reset Sample, "RS"

(CDS=1, CDSREF=01 )

Reset Sample, "RS"

(CDS=1, CDSREF=10 )

Reset Sample, "RS"

(CDS=1, CDSREF=11)

RLC switch control, "CL"

(CDSREF=00 )

RLC switch control, "CL"

(CDSREF=00 )

RLC switch control, "CL"

(CDSREF=00 )

RLC switch control, "CL"

(CDSREF=00 )

RLC sw closed

if RSMP=1

RSMP

t

LRSMPSU

t

LRSMPH

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

RLC sw closed

if RSMP=1

RLC sw closed

if RSMP=1

RLC sw closed

if RSMP=1

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

xx

x

xx

Video sample on

falling edge of VS

Reset sample on

falling edge of RS

Reset sample on

falling edge of RS

Reset sample on

falling edge of RS

Reset sample on

falling edge of RS

xx

x

xx xx

Figure 8 LEGACY Mode RLC and Sampling (LEGACY=1)