WM8214

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PP Rev 1.6 March 2004

18

CALCULATING THE OUTPUT CODE FOR A GIVEN INPUT

The following equations describe the processing of the video and reset level signals through the

PGA value is written first to set the input Voltage range, the Offset DAC is then adjusted

to compensate for any Black/Reset level offsets and finally the RLC DAC value is set to position the

reset level correctly during operation.

Note:

Refer to Applications Note WAN0123 for detailed information on device calibration

procedures.

INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING

input video.

=

Eqn. 1

If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted

instead.

=

Eqn. 2

=

Eqn. 3

OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST

=

∗ (DAC[7:0]-127.5) } / 127.5

Eqn. 4

PGA NODE: GAIN ADJUST

The signal is then multiplied by the PGA gain.

=

∗ (0.66 + PGA[8:0]x7.34/511)

Eqn. 5

ADC BLOCK: ANALOGUE-DIGITAL CONVERSION

The analogue signal is then converted to a 16-bit unsigned number, with input range configured by

PGAFS[1:0].

∗ 65535} + 32767

PGAFS[1:0] = 00 or 01

Eqn. 6

∗ 65535}

PGAFS[1:0] = 11

Eqn. 7

∗ 65535} + 65535

PGAFS[1:0] = 10

Eqn. 8

OUTPUT INVERT BLOCK: POLARITY ADJUST

The polarity of the digital output may be inverted by control bit INVOP.

Eqn. 9

(INVOP = 1)

Eqn. 10