WM8214SCDSSLASHR datasheet(30/35 Pages) WOLFSON

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WM8214

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PP Rev 1.6 March 2004

BIT

NAME(S)

DEFAULT

DESCRIPTION

LINEBYLINE

Selects line by line operation. Line by line operation is intended for use with

systems which operate one line at a time but with up to three colours shared

on that one output.

0 = normal operation,

1 = line by line operation.

When line by line operation is selected MONO is forced to 1 and CHAN[1:0] to

00 internally, ensuring that the correct internal timing signals are produced.

Green and Blue PGAs are also disabled to save power.

ACYC

When LINEBYLINE = 0 this bit has no effect.

When LINEBYLINE = 1 this bit determines the function of the RSMP input pin

and the offset/gain register controls.

0 = RSMP pin enabled for either reset sampling (CDS) or Reset Level Clamp

control. Internal selection of gain/offset multiplexers using INTM[1:0] register

bits.

1 = Auto-cycling enabled by pulsing the RSMP input pin. This means that

each time a pulse is applied to this pin the single input channel will switch to

the next offset and gain registers in the sequence. The sequence is

Red->Green->Blue->Red… offset and gain registers applied to the red input

channel.

When auto-cycling is enabled, the RSMP pin cannot be used to control reset

level clamping. The CLMPCTRL bit may be used instead (enabled when high,

disabled when low).

NB, when auto-cycling is enabled, the RSMP pin cannot be used for reset

sampling (i.e. CDS must be set to 0).

Setup

3:2

INTM[1:0]

When LINEBYLINE=0 or ACYC=0 this bit has no effect.

When LINEBYLINE=1 and ACYC=1:

Controls the PGA/offset mux selector:

00 = Red PGA/Offset registers applied to input channel

01 = Green PGA/Offset registers applied to input channel

10 = Blue PGA/Offset registers applied to input channel

11 = Reserved.

REDPD

When set powers down red S/H, PGA

GRNPD

When set powers down green S/H, PGA

BLUPD

When set powers down blue S/H, PGA

ADCPD

When set powers down ADC. Allows reduced power consumption without

powering down the references which have a long time constant when

switching on/off due to the external decoupling capacitors.

RLCCDACPD

When set powers down 4-bit RLCDAC, setting the output to a high impedance

state and allowing an external reference to be driven in on the VRLC/VBIAS

pin.

ADCREFPD

When set disables VRT, VRB buffers to allow external references to be used.

Setup

VRXPD

When set disables VRX buffer to allow an external reference to be used.

VSMPDET

When LEGACY=0 this register bit has no effect.

When LEGACY=1:

0 = Normal operation, signal on VSMP input pin is applied directly to Timing

Control block.

1 = Programmable VSMP detect circuit is enabled. An internal synchronisation

pulse is generated from signal applied to VSMP input pin and is applied to

Timing Control block in place of VSMP.

Setup

3:1

VDEL[2:0]

000

When LEGACY=0 or VSMPDET=0 these bits have no effect.

The VDEL bits set a programmable delay from the detected edge of the signal

applied to the VSMP pin. The internally generated pulse is delayed by VDEL

MCLK periods from the detected edge.

See Figure 17, Internal VSMP Pulses Generated for details.

WM8214SCDS/R 数据表(PDF) 30 Page - Wolfson Microelectronics plc

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WM8214SCDS/R 数据表(PDF) 30 Page - Wolfson Microelectronics plc

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