WM8214SCDSSLASHR datasheet(29/35 Pages) WOLFSON

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WM8214

PP Rev 1.6 March 2004

BIT

NAME(S)

DEFAULT

DESCRIPTION

1:0

OPFORM[1:0]

Determines the output data format.

x0 = 8-bit multiplexed (8+8 bits)

01 = 8-bit parallel (8-MSBs only)

11 = 4-bit multiplexed mode (4+4+4+4 bits). This mode is only valid when

LEGACY=1.

INVOP

Digitally inverts the polarity of output data.

0 = negative going video gives negative going output,

1 = negative-going video gives positive going output data.

Output Disable. This works with the OEB pin to control the output pins.

0=Digital outputs enabled, 1=Digital outputs high impedance

OEB (pin)

OPD

OP pins

Enabled

High Impedance

OPD

High impedance

LOWREFS

Reduces the ADC reference range (2*[VRT-VRB]), thus changing the max/min

input voltages.

0= ADC reference range = 2.0V

1= ADC reference range = 1.2V

RLCDACRNG

Sets the output range of the RLCDAC.

0 = RLCDAC ranges from 0 to AVDD (approximately),

1 = RLCDAC ranges from 0 to VRT (approximately).

Controls the latency from sample to data appearing on output pins

Latency

DEL

LEGACY=0

All timing modes

LEGACY=1

timing modes 1-2,4-6

LEGACY=1

timing mode 3

7 MCLK periods

16.5 MCLK periods

23.5 MCLK periods

8 MCLK periods

18.5 MCLK periods

26.5 MCLK periods

9 MCLK periods

20.5 MCLK periods

29.5 MCLK periods

Setup

7:6

DEL[1:0]

10 MCLK periods

22.5 MCLK periods

31.5 MCLK periods

3:0

RLCDAC[3:0]

1111

Controls RLCDAC driving VRLC/VBIAS pin to define single ended signal

reference voltage or Reset Level Clamp voltage. See Electrical Characteristics

section for ranges.

5:4

CDSREF[1:0]

When LEGACY=0 these register bits have no effect.

CDS mode reset timing adjust.

00 = Advance reset sample by 1 MCLK period (relative to default).

01 = Default reset sample position.

10 = Delay reset sample by 1 MCLK period (relative to default)

11 = Delay reset sample by 2 MCLK periods (relative to default)

When MONO=0 these register bits have no effect

Monochrome mode channel select.

Setup

7:6

CHAN[1:0]

00 = Red channel select

01 = Green channel select

10 = Blue channel select

11 = Reserved

Software

Reset

Any write to Software Reset causes all cells to be reset. It is recommended

that a software reset be performed after a power-up before any other register

writes.

Auto-cycle

Reset

Any write to Auto-cycle Reset causes the auto-cycle counter to reset

to RINP. This function is only required when LINEBYLINE = 1.

WM8214SCDS/R 数据表(PDF) 29 Page - Wolfson Microelectronics plc

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