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WM8214SCDS/R 数据表(PDF) 31 Page - Wolfson Microelectronics plc

部件名 WM8214SCDS/R
功能描述  40MSPS 16 BIT CCD DIGITISER
PDF  35 Pages
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制造商  WOLFSON [Wolfson Microelectronics plc]
网页  http://www.wolfsonmicro.com
标志 WOLFSON - Wolfson Microelectronics plc

WM8214SCDS/R 数据表(HTML) 31 Page - Wolfson Microelectronics plc

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WM8214
w
PP Rev 1.6 March 2004
31
REGISTER
BIT
NO
BIT
NAME(S)
DEFAULT
DESCRIPTION
4
POSNNEG
0
When LEGACY=0 or VSMPDET=0 this bit has no effect.
When LEGACY=1 and VSMPDET=1 this bit controls whether positive or
negative edges on the VSMP input pin are detected:
0 = Negative edge on VSMP pin is detected and used to generate internal
timing pulse.
1 = Positive edge on VSMP pin is detected and used to generate internal
timing pulse.
See Figure 17 for further details.
5
RLCEN
1
Reset Level Clamp Enable. When set Reset Level Clamping is enabled. The
method of clamping is determined by CLAMPCTRL and LEGACY.
In LEGACY mode clamping will still occur on every pixel at a time defined by
the CDSREF[1:0] bits.
6
CLAMPCTRL
0
This bit has no effect if LEGACY=1. See Table 1 for more information.
0 = RLC switch is controlled directly from RSMP input pin:
RSMP = 0: switch is open
RMSP = 1: switch is closed
1 = RLC switch is controlled by logical combination of RSMP and VSMP.
RSMP && VSMP = 0: switch is open
RSMP && VSMP = 1: switch is closed
Offset DAC
(Red)
7:0
DACR[7:0]
0
Red channel 8-bit offset DAC value (mV) = 260*(DACR[7:0]-127.5)/127.5
Offset DAC
(Green)
7:0
DACG[7:0]
0
Green channel 8-bit offset DAC value (mV) = 260*(DACG[7:0]-127.5)/127.5
Offset DAC
(Blue)
7:0
DACB[7:0]
0
Blue channel 8-bit offset DAC value (mV) = 260*(DACB[7:0]-127.5)/127.5
Offset DAC
(RGB)
7:0
DACRGB[7:0]
0
A write to this register location causes the red, green and blue offset DAC
registers to be overwritten by the new value
PGA Gain
LSB
(Red)
0
PGAR[0]
0
This register bit forms the LSB of the red channel PGA gain code. PGA gain
is determined by combining this register bit and the 8 MSBs contained in
register address 28 hex.
PGA Gain
LSB
(Green)
0
PGAG[0]
0
This register bit forms the LSB of the green channel PGA gain code. PGA
gain is determined by combining this register bit and the 8 MSBs contained in
register address 29 hex.
PGA Gain
LSB
(Blue)
0
PGAB[0]
0
This register bit forms the LSB of the blue channel PGA gain code. PGA gain
is determined by combining this register bit and the 8 MSBs contained in
register address 2A hex.
PGA Gain
LSB
(RGB)
0
PGARGB[0]
0
Writing a value to this location causes red, green and blue PGA LSB gain
values to be overwritten by the new value.
PGA gain
MSBs
(Red)
7:0
PGAR[8:1]
0D
Bits 8 to 1 of red PGA gain. Combined with red LSB register bit to form
complete PGA gain code. This determines the gain of the red channel PGA
according to the equation:
Red channel PGA gain (V/V) = 0.66 + PGAR[8:0]x7.34/511
PGA gain
MSBs
(Green)
7:0
PGAG[8:1]
0D
Bits 8 to 1 of green PGA gain. Combined with green LSB register bit to form
complete PGA gain code. This determines the gain of the green channel PGA
according to the equation:
Green channel PGA gain (V/V) = 0.66 + PGAG[8:0]x7.34/511
PGA gain
MSBs
(Blue)
7:0
PGAB[8:1]
0D
Bits 8 to 1 of blue PGA gain. Combined with blue LSB register bit to form
complete PGA gain code. This determines the gain of the blue channel PGA
according to the equation:
BLue channel PGA gain (V/V) = 0.66 + PGAB[8:0]x7.34/511
PGA gain
MSBs
(RGB)
7:0
PGARGB[8:1]
0
A write to this register location causes the red, green and blue PGA MSB gain
registers to be overwritten by the new value.
Table 5 Register Control Bits



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