WM8214

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PP Rev 1.6 March 2004

12

RESET LEVEL CLAMPING (RLC)

To ensure that the signal applied to the WM8214 lies within the supply voltage range (0V to AVDD)

circuit clamps the WM8214 side of this capacitor to a suitable voltage through a CMOS switch during

the CCD reset period. In order for clamping to produce sensible results the input voltage during the

clamping must be a consistent value.

The WM8214 allows the user to control the RLC switch in a variety of ways as illustrated in Figure 5.

This figure shows a single channel, however all 3 channels are identical, each with its own clamp

switch controlled by the common CLMP signal.

The method of control chosen depends upon the characteristics of the input video. The RLCEN

register bit must be set to 1 to enable clamping, otherwise the RLC switch cannot be closed (by

default RLCEN=1).

CONTROL

INTERFACE

MCLK

VSMP

RSMP

C

IN

RINP

or

GINP

or

BINP

VRLC/

VBIAS

CDACEN

1

0

LEGACY

RLCEN

4-BIT

CDAC

CDAC[4:0]

closed=

50 Ohm

1

0

CLAMPCTRL

0

1

LINEBYLINE

ACYC

LEGACY

TIMING

CL

RLC/ACYC

VSMP

MCLK

EN

RLC

switch

CLMP

Figure 5 RLC Clamp Control Options

When an input waveform has a stable reference level on every pixel it may be desirable to clamp

every pixel during this period. Setting CLMPCTRL=1 means that the RLC switch is closed whenever

the RSMP input pin is high, as shown in Figure 6.

MCLK

VSMP

RSMP

RLC switch control

"CLMP"

(RLCEN=1,CLMPCTRL=0)

RLC switch closed

when RSMP=1

Video sample taken on

fallling edge of VSMP

Reset/reference sample taken

on fallling edge of RSMP

INPUT VIDEO

SIGNAL

reference

("black") level

video level

Figure 6 Reset Level Clamp Operation (CLMPCTRL=0), CDS operation shown, non-CDS also possible