Application information

ST1S31

20/35

DocID022998 Rev 4

Equation 27

calculated as the parallel of many paths of heat conduction from the junction to the ambient.

For this device the path through the exposed pad is the one conducting the largest amount

50 °C/W for the VFDFPN and 100 °C/W for the SO8 package.

Figure 9. Switching losses

5.5

Layout consideration

The PC board layout of the switching DC-DC regulator is very important to minimize the

noise injected in high impedance nodes, to reduce interference generated by the high

switching current loops and to optimize the reliability of the device.

In order to avoid EMC problems, the high switching current loops must be as short as

possible. In the buck converter there are two high switching current loops: during the

on-time, the pulsed current flows through the input capacitor, the high-side power switch,

the inductor and the output capacitor; during the off-time, through the low-side power switch,

the inductor and the output capacitor.

The input capacitor connected to VINSW must be placed as close as possible to the device,

to avoid spikes on VINSW due to the stray inductance and the pulsed input current.

In order to prevent dynamic unbalance between VINSW and VINA, the trace connecting the

VINA pin to the input must be derived from VINSW.



+

=

AM11422v1