PC87311AVF datasheet(3/78 Pages) NSC

3 / 78 page

Table of Contents

634 Line Status Register (LSR)

635 FIFO Control Register (FCR)

636 Interrupt Identification Register (IIR)

637 Interrupt Enable Register (IER)

638 MODEM Control Register (MCR)

639 MODEM Status Register (MSR)

6310 Scratchpad Register (SCR)

70 PARALLEL PORT

71 Introduction

72 Data Register (DTR)

73 Status Register (STR)

74 Control Register (CTR)

80 INTEGRATED DEVICE ELECTRONICS

INTERFACE (IDE)

81 Introduction

82 IDE Signals

90 DEVICE DESCRIPTION

91 DC Electrical Characteristics

92 AC Electrical Characteristics

921 AC Test Conditions

922 Clock Timing

923 Microprocessor Interface Timing

924 Baudout Timing

925 Transmitter Timing

926 Receiver Timing

927 MODEM Control Timing

928 DMA Timing

929 Reset Timing

9210 Write Data Timing

9211 Drive Control Timing

9212 Read Data Timing

9213 IDE Timing

9214 Parallel Port Timing

100 REFERENCE SECTION

101 Mnemonic Definitions for FDC Commands

102 Example Four Drive Circuit

Using the PC87311A12

List of Figures

FIGURE 2-1

PC87311A87312 Configuration Registers

FIGURE 3-1

FDC Functional Block Diagram

FIGURE 4-1

IBM Perpendicular and ISO Formats Supported by Format Command

FIGURE 5-1

FDC Data Separator Block Diagram

FIGURE 5-2

PC87311A87312 Dynamic Window Margin Performance

FIGURE 5-3

Read Data AlgorithmState Diagram

FIGURE 5-4

Perpendicular Recording Drive RW Head and Pre-Erase Head

FIGURE 6-1

PC87311A Composite Serial Data

FIGURE 6-2

PC87312 Composite Serial Data

FIGURE 9-1

Clock Timing

FIGURE 9-2

Microprocessor Read Timing

FIGURE 9-3

Microprocessor Write Timing

FIGURE 9-4

Baudout Timing

FIGURE 9-5

Transmitter Timing

FIGURE 9-6a

Receiver Timing

FIGURE 9-6b

PC87312 FIFO Mode Receiver Timing

FIGURE 9-6c

PC87312 Timeout Receiver Timing

FIGURE 9-7

MODEM Control Timing

FIGURE 9-8

DMA Timing

FIGURE 9-9

Reset Timing

FIGURE 9-10

Write Data Timing

FIGURE 9-11

Drive Control Timing

FIGURE 9-12

Read Data Timing

FIGURE 9-13

IDE Timing

FIGURE 9-14

Parallel Port Interrupt Timing (Compatible Mode)

FIGURE 9-15

Parallel Port Interrupt Timing (Extended Mode)

FIGURE 9-16

Typical Parallel Port Data Exchange

FIGURE 10-1

PC87311A87312 Four Floppy Drive Circuit

FIGURE 10-2

IDE Interface Signal Equations

FIGURE 10-3

PC87311A87312 Adapter Card Schematic

PC87311AVF 数据表(PDF) 3 Page - National Semiconductor (TI)

PC87311AVF 数据表(HTML) 3 Page - National Semiconductor (TI)

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