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PC87311AVF 数据表(PDF) 68 Page - National Semiconductor (TI) |
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PC87311AVF 数据表(HTML) 68 Page - National Semiconductor (TI) |
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68 / 78 page ![]() 90 Device Description (Continued) 926 Receiver Timing Symbol Parameter Conditions Min Max Units tRAI Delay from Active Edge of RD to Reset IRQ 78 ns tRINT Delay from Inactive Edge of RD (RD LSR) to Reset IRQ 40 ns tSCD Delay from RCLK to Sample Time (Note 1) 41 ns tSINT Delay from Stop Bit to Set Interrupt 2 BAUDOUT Cycles Note 1 This is an internal timing and is therefore not tested TLF11362 – 22 FIGURE 9-6a Receiver Timing TLF11362 – 23 Note 2 If SCR0 e 1 then tSINT e 3 RCLKs For a Timeout interrupt tSINT e 8 RCLKs FIGURE 9-6b PC87312 FIFO Mode Receiver Timing 68 |
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