PC87311AVF datasheet(20/78 Pages) NSC

20 / 78 page

30 FDC Register Description (Continued)

Read Data

Active high status of latched RDATA

signal This bit is latched by the inactive going edge

of RDATA and is cleared by a read from the DIR

Write Gate

Active high status of latched WGATE

signal This bit is latched by the active going edge of

WGATE and is cleared by a read from the DIR

Drive Select 3

Active low status of the DR3 disk

interface output (Note 1)

Drive Select 2

Active low status of the DR2 disk

interface output (Note 1)

33 DIGITAL OUTPUT REGISTER (DOR)

ReadWrite

The DOR controls the drive select and motor enable disk

interface outputs enables the DMA logic and contains a

software reset bit The content of the DOR is set to 00 (hex)

after a hardware reset and is unaffected by a software re-

set (Note 2)

DOR

DESC

MTR3 MTR2 MTR1 MTR0 DMAEN RESET

DRIVE DRIVE

SEL 1

SEL 0

RESET

0000

COND

Motor Enable 3

This bit controls the MTR3 disk

interface output A1in this bit causes the MTR3 pin

to go active (Note 1)

Motor Enable 2

Same function as D7 except for

MTR2 (Note 1)

Motor Enable 1

Same function as D7 except for

MTR1

Motor Enable 0

Same function as D7 except for

MTR0

DMA Enable

This bit has two modes of operation

PC-AT mode or Model 30 mode

Writinga1to this

bit will enable the DRQ DACK TC and IRQ6 pins

Writinga0to this bit will disable the DACK and TC

pins and TRI-STATE the DRQ and the IRQ6 pins

This bit is a 0 after a reset when in these modes

PS2 mode

This bit is reserved and the DRQ

DACK TC and IRQ6 pins will always be enabled

During a reset the DRQ DACK TC and IRQ6 lines

will remain enabled and D3 will be a 0

Reset Controller

Writinga0to this bit resets the

controller It will remain in the reset condition until a

1 is written to this bit A software reset does not

affect the DSR CCR and other bits of the DOR A

software reset will affect the Configure and Mode

command bits (see Section 40 Command Set De-

scription) The minimum time that this bit must be

low is 100 ns Thus toggling the Reset Controller bit

during consecutive writes to the DOR is an accept-

able method of issuing a software reset

D1D0 Drive Select

These two bits are binary encoded for

the four drive selects DR0 – DR3 so that only one

drive select output is active at a time (Note 1)

It is common programming practice to enable both the mo-

tor enable and drive select outputs for a particular drive

Table 3-2 below shows the DOR values to enable each of

the four drives

TABLE 3-2 Drive Enable Values

Drive

DOR Value

1C (hex)

12D

24E

38F

34 TAPE DRIVE REGISTER (TDR)

ReadWrite

This register is used to assign a particular drive number with

the tape drive support mode of the data separator All other

logical drives are assigned floppy drive support with the

data separator Any future reference to the assigned tape

drive will invoke tape drive support The TDR is unaffected

by a software reset

TDR

DESC

XXXXXX

TAPE

SEL 1

SEL 0

RESET

COND

D7 – D2 Reserved

These bits are ignored when written to

and are TRI-STATE when read

D1D0 Tape Select 10

These two bits assign a logical

drive number to be a tape drive Drive 0 is not avail-

able as a tape drive and is reserved as the floppy

disk boot drive See Table 3-3 for the tape drive

assignment values

TABLE 3-3 Tape Drive Assignment Values

TAPESEL1

TAPESEL0

Drive

Selected

None

35 MAIN STATUS REGISTER (MSR)

Read Only

The read-only Main Status Register indicates the current

status of the disk controller The Main Status Register is

always available to be read One of its functions is to control

the flow of data to and from the Data Register (FIFO) The

Main Status Register indicates when the disk controller is

ready to send or receive data through the Data Register It

should be read before each byte is transferred to or from

the Data Register except during a DMA transfer No delay is

required when reading this register after a data transfer

Note 1

The MTR3 MTR2 DRV3 DRV2 pins are only available in 4-drive mode (FER4 e 1) and require external logic

Note 2

The DOR can be written to at any time but only one drive select output in conjunction with its corresponding motor is active at a time

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