PC87311AVF datasheet(21/78 Pages) NSC

21 / 78 page

30 FDC Register Description (Continued)

After a hardware or software reset or recovery from a pow-

er down state the Main Status Register is immediately avail-

able to be read by the mP It will contain a value of 00 hex

until the oscillator circuit has stabilized and the internal reg-

isters have been initialized When the FDC is ready to re-

ceive a new command it will report an 80 hex to the mP

The system software can poll the MSR until it is ready The

worst case time allowed for the MSR to report an 80 hex

value (RQM set) is 25 ms after reset or power up

MSR

DESC

RQM

DIO

NON

CMD

DRV3

DRV2

DRV1

DRV0

DMA

PROG

BUSY

RESET

0000

COND

Request for Master

Indicates that the controller is

ready to send or receive data from the mP through

the FIFO This bit is cleared immediately after a byte

transfer and will become set again as soon as the

disk controller is ready for the next byte During a

Non-DMA Execution phase the RQM indicates the

status of the interrupt pin

Data IO (Direction)

Indicates whether the con-

troller is expecting a byte to be written to (0) or read

from (1) the Data Register

Non-DMA Execution

Indicates that the controller

is in the Execution Phase of a byte transfer opera-

tion in the Non-DMA mode Used for multiple byte

transfers by the mP in the Execution Phase through

interrupts or software polling

Command in Progress

This bit is set after the first

byte of the Command Phase is written This bit is

cleared after the last byte of the Result Phase is

read If there is no Result Phase in a command the

bit is cleared after the last byte of the Command

Phase is written

Drive 3 Busy

Set after the last byte of the Com-

mand Phase of a Seek or Recalibrate command is

issued for drive 3 Cleared after reading the first

byte in the Result Phase of the Sense Interrupt

Command for this drive

Drive 2 Busy

Same as above for drive 2

Drive 1 Busy

Same as above for drive 1

Drive 0 Busy

Same as above for drive 0

36 DATA RATE SELECT REGISTER (DSR)

Write Only

This write-only register is used to program the data rate

amount of write precompensation power down mode and

software reset The data rate is programmed via the CCR

not the DSR for PC-AT and PS2 Model 30 and MicroChan-

nel applications Other applications can set the data rate in

the DSR The data rate of the floppy controller is deter-

mined by the most recent write to either the DSR or CCR

The DSR is unaffected by a software reset A hardware re-

set will set the DSR to 02 (hex) which corresponds to the

default precompensation setting and 250 kbs

DSR

DESC

LOW

PRE-

DRATE1 DRATE0

RESET POWER

COMP2 COMP1 COMP0

RESET

COND

Software Reset

This bit has the same function as

the DOR RESET (D2) except that this software re-

set is self-clearing

Low Power

A 1 to this bit will put the controller into

the Manual Low Power mode The oscillator and

data separator circuits will be turned off Manual

Low Power can also be accessed via the Mode

command The chip will come out of low power after

a software reset or access to the Data Register or

Main Status Register

Undefined Should be set to 0

D4 – D2 Precompensation Select

These three bits select

the amount of write precompensation the floppy

controller will use on the WDATA disk interface out-

put Table 3-4 shows the amount of precompensa-

tion used for each bit pattern In most cases the

default values (Table 3-5) can be used however

alternate values can be chosen for specific types of

drives and media Track 0 is the default starting

track number for precompensation The starting

track number can be changed in the Configure com-

mand

TABLE 3-4 Write Precompensation Delays

Precomp 432

Precompensation Delay

111

00 ns

001

417 ns

010

833 ns

011

1250 ns

100

1667 ns

101

2083 ns

110

2500 ns

000

DEFAULT

TABLE 3-5 Default Precompensation Delays

Data Rate

Precompensation Delay

1 Mbs

417 ns

500 kbs

1250 ns

300 kbs

1250 ns

250 kbs

1250 ns

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