PC87311AVF datasheet(8/78 Pages) NSC

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10 Pin Description (Continued)

Symbol

Function

DR01

44 45

Drive Select 01

These are the decoded drive select outputs that are controlled by Digital Output

outputs They are encoded with information to control four FDDs when bit 4 of the Function Enable

DRATE01

52 51

Data Rate 01

These outputs reflect the currently selected FDC data rate (bits 0 and 1 in the

Configuration Control Register (CCR) or the Data Rate Select Register (DSR) whichever was written

to last) These pins are totem-pole buffered outputs (6 mA sink 6 mA source)

DRQ

DMA Request

Active high output to signal the DMA controller that a FDC data transfer is needed

When in PC-AT or Model 30 mode this signal is enabled by bit D3 of the DOR When in PS2 mode

DRQ is always enabled and bit D3 of the DOR is reserved

DRV2

Drive2

This input indicates whether a second disk drive has been installed The state of this pin is

available from Status Register A in PS2 mode

DSKCHG

Disk Change

The input indicates if the drive door has been opened The state of this pin is available

from the Digital Input register This pin can also be configured as the RGATE data separator

diagnostic input via the Mode command (see Section 426)

DSR12

76 68

Data Set Ready

When low this indicates that the data set or MODEM is ready to establish a

communications link The DSR signal is a MODEM status input whose condition the CPU can test by

reading bit 5 (DSR) of the MODEM Status Register (MSR) for the appropriate channel Bit 5 is the

complement of the DSR signal Bit 1 (DDSR) of the MSR indicates whether the DSR input has

changed state since the previous reading of the MSR

Note

Whenever the DDSR bit of the MSR is set an interrupt is generated if MODEM Status interrupts are enabled

DTR12

71 63

Data Terminal Ready

When low this output indicates to the MODEM or data set that the UART is

ready to establish a communications link The DTR signal can be set to an active low by programming

bit 0 (DTR) of the MODEM Control Register to a high level A Master Reset operation sets this signal

to its inactive (high) state In the PC87312 loop mode operation holds this signal to its inactive state

(See CFG4 – 0 for further information) In the PC87311A loop mode operation holds this signal to its

inactive state if the XTSEL pin is high during reset If the XTSEL pin is low during reset the associated

pin state is controlled by the MCR0 bit during loop mode operation (See XTSEL and CFG0 – 4 for

further information)

ERR

Error

This input is set low by the printer when it has detected an error This pin has nominal 25 kX

pull-up resistor attached to it

HCS0

Hard Drive Chip Select 0

This output is active in the AT mode when the hard drive registers from

1F0 – 1F7h are selected if the primary address is used or when 170 – 177h are selected if the

secondary address is used In the XT mode (PC87311A) this output is active if the addresses from

320 – 324h are selected This output is inactive if the IDE interface is disabled via the Configuration

HCS1

Hard Drive Chip Select 1

This output is active in the AT mode when the hard drive registers from

3F6 – 7 are selected if the primary address is used or when 376 – 377 are selected if the secondary

address is used In the XT mode (PC87311A) this output is inactive This output is also inactive if the

IDE interface is disabled via the Configuration Register (See PDIR for further information)

HDSEL

Head Select

This output determines which side of the FDD is accessed Active selects side 1

inactive selects side 0

IDED7

IDE Bit 7

This pin provides the data bus bit 7 signal to the IDE hard drive during accesses in the

address range 1F0 – 1F7h 170 – 177h and 3F6h and 376h This pin is TRI-STATE during read or write

accesses to 3F7h and 377h

IDEHI

IDE High Byte

This output enables the high byte data latch during a read or write to the hard drive if

the hard drive returns IOCS16 This output is inactive if the IDE interface is disabled via the

Configuration Register

IDELO

IDE Low Byte

This output enables the low byte data latch during a read or write to the hard drive

This output is inactive if the IDE interface is disabled via the Configuration Register (See BADDR0 for

further information)

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