TNETV2685FIBZUT7 datasheet(111/191 Pages) TI1

111 / 191 page

TMS320DM647

TMS320DM648

www.ti.com

SPRS372H – MAY 2007 – REVISED APRIL 2012

6.10 External Memory Interface A (EMIFA)

The EMIFA can interface to a variety of external devices or ASICs, including:

•

Pipelined and flow-through synchronous-burst SRAM (SBSRAM)

•

ZBT (zero bus turnaround) SRAM and late write SRAM

•

Synchronous FIFOs

•

Asynchronous memory, including SRAM, ROM, and Flash

6.10.1 EMIFA Device-Specific Information

Timing analysis must be done to verify all ac timing requirements are met. TI recommends utilizing I/O

buffer information specification (IBIS) to analyze all ac timing.

To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS

Models for Timing Analysis Application Report (literature number SPRA839).

To maintain signal integrity, serial termination resistors should be inserted into all EMIFA output signal

lines.

A race condition may exist when certain masters write data to the EMIFA. For example, if master A

passes a software message via a buffer in external memory and does not wait for indication that the write

completes, when master B attempts to read the software message, then the master B read may bypass

the master A write and, thus, master B may read stale data and, therefore, receive an incorrect message.

Some master peripherals (e.g., EDMA3 transfer controllers) will always wait for the write to complete

before signaling an interrupt to the system, thus avoiding this race condition. For masters that do not have

hardware specification of write-read ordering, it may be necessary to specify data ordering via software.

If master A does not wait for indication that a write is complete, it must perform the following workaround:

1. Perform the required write.

2. Perform a dummy write to the EMIFA module ID and revision register.

3. Perform a dummy read to the EMIFA module ID and revision register.

4. Indicate to master B that the data is ready to be read after completion of the read in step 3. The

completion of the read in step 3 ensures that the previous write was done.

6.10.2 EMIFA Peripheral Register Description(s)

For more information on the EMIF registers shown in Table 6-41, see TMS320DM647/DM648 DSP

External Memory Interface (EMIF) User's Guide (literature number SPRUEK6).

Table 6-41. EMIFA Registers

HEX ADDRESS RANGE

ACRONYM

0x7000 0000

MIDR

Module ID and Revision Register

0x7000 0004

STAT

Status Register

0x7000 0008

Reserved

0x7000 000C - 0x7000 001C

Reserved

0x7000 0020

BPRIO

Burst Priority Register

0x7000 0024 - 0x7000 004C

Reserved

0x7000 0050 - 0x7000 007C

Reserved

0x7000 0080

CE2CFG

EMIFA CE2 Configuration Register

0x7000 0084

CE3CFG

EMIFA CE3 Configuration Register

0x7000 0088

Reserved

0x7000 008C

Reserved

0x7000 0090 - 0x7000 009C

Reserved

0x7000 00A0

AWCC

EMIFA Async Wait Cycle Configuration Register

Peripheral Information and Electrical Specifications

111

Submit Documentation Feedback

Product Folder Link(s): TMS320DM647 TMS320DM648

TNETV2685FIBZUT7 数据表(PDF) 111 Page - Texas Instruments

TNETV2685FIBZUT7 数据表(HTML) 111 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

TNETV2685FIBZUT7 数据表(PDF) 111 Page - Texas Instruments

TNETV2685FIBZUT7 数据表(HTML) 111 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载