TNETV2685FIBZUT7 datasheet(116/191 Pages) TI1

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AECLKOUT

ACEx

ABE[7:0]

AEA[19:0]/ABA[1:0]

AED[63:0]

ASADS/ASRE(B)

AAOE /ASOE(B)

AAWE/ASWE(B)

BE1

BE2

BE3

BE4

BE1

BE2

BE3

BE4

EA1

EA2

EA4

READ latency = 2

EA3

AECLKOUT

ACEx

ABE[1:0]

AEA[23:0]/ABA[1:0]

AED[15:0]

ASADSASRE

AAOEASOE

AAWEASWE

BE1

BE2

BE3

BE4

EA1

EA2

EA3

EA4

TMS320DM647

TMS320DM648

SPRS372H – MAY 2007 – REVISED APRIL 2012

www.ti.com

Figure 6-24. Programmable Synchronous Interface Read Timing for EMIFA (With Read Latency = 2)

NOTE

This information applies to Figure 6-25 and Figure 6-26.

The following parameters are programmable via the EMIF Chip Select n Configuration

•

Read latency (R_LTNCY): 1-, 2-, or 3-cycle read latency

•

Write latency (W_LTNCY): 0-, 1-, 2-, or 3-cycle write latency

•

ACEx assertion length (CE_EXT): For standard SBSRAM or ZBT SRAM interface, ACEx

goes inactive after the final command has been issued (CE_EXT = 0). For synchronous

FIFO interface, ACEx is active when AAOE/ASOE is active (CE_EXT = 1).

•

Function of ASADS/ASRE (R_ENABLE): For standard SBSRAM or ZBT SRAM interface,

ASADS/ASRE has deselect cycles (R_ENABLE = 0). For FIFO interface, ASADS/ASRE

has NO deselect cycles (R_ENABLE = 1).

In this figure, W_LTNCY = 0, CE_EXT = 0, R_ENABLE = 0, and SSEL = 1.

Figure 6-25. Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 0)

116

Peripheral Information and Electrical Specifications

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