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TNETV2685FIBZUT7 数据表(PDF) 120 Page - Texas Instruments |
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TNETV2685FIBZUT7 数据表(HTML) 120 Page - Texas Instruments |
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120 / 191 page  TMS320DM647 TMS320DM648 SPRS372H – MAY 2007 – REVISED APRIL 2012 www.ti.com Table 6-48. Video Port 0, 1, 2, 3, and 4 (VP0, VP1, VP2, VP3, and VP4) Control Registers (continued) HEX ADDRESS RANGE ACRONYM DESCRIPTION VP0 VP1 VP2 VP3 VP4 Video Display Field 1 Image Offset 0x02C0 0220 0x02C0 4220 0x02C0 8220 0x02C0 C220 0x02C1 0220 VDIMGOFF1 Register Video Display Field 1 Image Size 0x02C0 0224 0x02C0 4224 0x02C0 8224 0x02C0 C224 0x02C1 0224 VDIMGSZ1 Register Video Display Field 2 Image Offset 0x02C0 0228 0x02C0 4228 0x02C0 8228 0x02C0 C228 0x02C1 0228 VDIMGOFF2 Register Video Display Field 2 Image Size 0x02C0 022C 0x02C0 422C 0x02C0 822C 0x02C0 C22C 0x02C1 022C VDIMGSZ2 Register 0x02C0 0230 0x02C0 4230 0x02C0 8230 0x02C0 C230 0x02C1 0230 VDFLDT1 Video Display Field 1 Timing Register 0x02C0 0234 0x02C0 4234 0x02C0 8234 0x02C0 C234 0x02C1 0234 VDFLDT2 Video Display Field 2 Timing Register 0x02C0 0238 0x02C0 4238 0x02C0 8238 0x02C0 C238 0x02C1 0238 VDTHRLD Video Display Threshold Register Video Display Horizontal Synchronization 0x02C0 023C 0x02C0 423C 0x02C0 823C 0x02C0 C23C 0x02C1 023C VDHSYNC Register Video Display Field 1 Vertical 0x02C0 0240 0x02C0 4240 0x02C0 8240 0x02C0 C240 0x02C1 0240 VDVSYNS1 Synchronization Start Register Video Display Field 1 Vertical 0x02C0 0244 0x02C0 4244 0x02C0 8244 0x02C0 C244 0x02C1 0244 VDVSYNE1 Synchronization End Register Video Display Field 2 Vertical 0x02C0 0248 0x02C0 4248 0x02C0 8248 0x02C0 C248 0x02C1 0248 VDVSYNS2 Synchronization Start Register Video Display Field 2 Vertical 0x02C0 024C 0x02C0 424C 0x02C0 824C 0x02C0 C24C 0x02C1 024C VDVSYNE2 Synchronization End Register 0x02C0 0250 0x02C0 4250 0x02C0 8250 0x02C0 C250 0x02C1 0250 VDRELOAD Video Display Counter Reload Register 0x02C0 0254 0x02C0 4254 0x02C0 8254 0x02C0 C254 0x02C1 0254 VDDISPEVT Video Display Event Register 0x02C0 0258 0x02C0 4258 0x02C0 8258 0x02C0 C258 0x02C1 0258 VDCLIP Video Display Clipping Register Video Display Default Display Value 0x02C0 025C 0x02C0 425C 0x02C0 825C 0x02C0 C25C 0x02C1 025C VDDEFVAL Register 0x02C0 0260 0x02C0 4260 0x02C0 8260 0x02C0 C260 0x02C1 0260 VDVINT Video Display Vertical Interrupt Register 0x02C0 0264 0x02C0 4264 0x02C0 8264 0x02C0 C264 0x02C1 0264 VDFBIT Video Display Field Bit Register Video Display Field 1Vertical Blanking Bit 0x02C0 0268 0x02C0 4268 0x02C0 8268 0x02C0 C268 0x02C1 0268 VDVBIT1 Register Video Display Field 2Vertical Blanking Bit 0x02C0 026C 0x02C0 426C 0x02C0 826C 0x02C0 C26C 0x02C1 026C VDVBIT2 Register 0x5000 0000 0x5400 0000 0x5800 0000 0x6000 0000 0x6400 0000 YSRCA Y FIFO Source Register A 0x5000 0020 0x5400 0020 0x5800 0020 0x6000 0020 0x6400 0020 CBSRCA CB FIFO Source Register A 0x5000 0040 0x5400 0040 0x5800 0040 0x6000 0040 0x6400 0040 CRSRCA CR FIFO Source Register A 0x5000 0080 0x5400 0080 0x5800 0080 0x6000 0080 0x6400 0080 YDSTA Y FIFO Destination Register A 0x5000 00A0 0x5400 00A0 0x5800 00A0 0x6000 00A0 0x6400 00A0 CBDST CB FIFO Destination Register 0x5000 00C0 0x5400 00C0 0x5800 00C0 0x6000 00C0 0x6400 00C0 CRDST CR FIFO Destination Register 0x5200 0000 0x5600 0000 0x5A00 0000 0x6200 0000 0x6600 0000 YSRCB Y FIFO Source Register B 0x5200 0020 0x5600 0020 0x5A00 0020 0x6200 0020 0x6600 0020 CBSRCB CB FIFO Source Register B 0x5200 0040 0x5600 0040 0x5A00 0040 0x6200 0040 0x6600 0040 CRSRCB CR FIFO Source Register B 0x5200 0080 0x5600 0080 0x5A00 0080 0x6200 0080 0x6600 0080 YDSTB Y FIFO Destination Register B 120 Peripheral Information and Electrical Specifications Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM647 TMS320DM648 |
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