ENICSF2811PBKA datasheet(21/172 Pages) TI1

21 / 172 page

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

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SPRS174T – APRIL 2001 – REVISED MAY 2012

Table 2-2. Signal Descriptions(1) (continued)

PIN NO.

NAME

I/O/Z(2)

PU/PD(3)

DESCRIPTION

179-BALL

176-PIN

128-PIN

GHH/ZHH

PGF

PBK

Emulator pin 1. When TRST is driven high,

this pin is used as an interrupt to or from the

emulator system and is defined as input/output

through the JTAG scan. This pin is also used

to put the device into boundary-scan mode.

With the EMU0 pin at a logic-high state and

the EMU1 pin at a logic-low state, a rising

edge on the TRST pin would latch the device

into boundary-scan mode.

EMU1

146

105

I/O/Z

NOTE: An external pullup resistor is

recommended on this pin. The value of this

resistor should be based on the drive strength

of the debugger pods applicable to the design.

A 2.2-k

Ω to 4.7-kΩ resistor is generally

adequate. Since this is application-specific, it

is recommended that each target board be

validated for proper operation of the debugger

and the application.

ADC ANALOG INPUT SIGNALS

ADCINA7

167

119

–

ADCINA6

168

120

–

ADCINA5

169

121

–

8-channel analog inputs for

ADCINA4

170

122

–

Sample-and-Hold A. The ADC pins should not

be driven before the VDDA1, VDDA2, and VDDAIO

ADCINA3

171

123

–

pins have been fully powered up.

ADCINA2

172

124

–

ADCINA1

173

125

–

ADCINA0

174

126

–

ADCINB7

–

ADCINB6

–

ADCINB5

–

8-channel analog inputs for

ADCINB4

–

Sample-and-Hold B. The ADC pins should not

be driven before the VDDA1, VDDA2, and VDDAIO

ADCINB3

–

pins have been fully powered up.

ADCINB2

–

ADCINB1

–

ADCINB0

–

ADC Voltage Reference Output (2 V).

Requires a low ESR (under 1.5

Ω) ceramic

bypass capacitor of 10 µF to analog ground.

[Can accept external reference input (2 V) if

the software bit is enabled for this mode.

ADCREFP

I/O

–

1–10 µF low ESR capacitor can be used in the

external reference mode.]

NOTE: Use the ADC Clock rate to derive the

ESR specification from the capacitor data

sheet that is used in the system.

ADC Voltage Reference Output (1 V).

Requires a low ESR (under 1.5

Ω) ceramic

bypass capacitor of 10 µF to analog ground.

[Can accept external reference input (1 V) if

the software bit is enabled for this mode.

ADCREFM

I/O

–

1–10 µF low ESR capacitor can be used in the

external reference mode.]

NOTE: Use the ADC Clock rate to derive the

ESR specification from the capacitor data

sheet that is used in the system.

Introduction

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