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ENICSF2811PBKA 数据表(PDF) 49 Page - Texas Instruments

部件名 ENICSF2811PBKA
功能描述  Digital Signal Processors
PDF  172 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

ENICSF2811PBKA 数据表(HTML) 49 Page - Texas Instruments

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TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
www.ti.com
SPRS174T – APRIL 2001 – REVISED MAY 2012
The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 3-15.
Table 3-15. PLL, Clocking, Watchdog, and Low-Power Mode Registers(1)
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
Reserved
0x00 7010 – 0x00 7017
8
Reserved
0x00 7018
1
Reserved
0x00 7019
1
High-Speed Peripheral Clock Prescaler Register for
HISPCP
0x00 701A
1
HSPCLK clock
Low-Speed Peripheral Clock Prescaler Register for
LOSPCP
0x00 701B
1
LSPCLK clock
PCLKCR
0x00 701C
1
Peripheral Clock Control Register
Reserved
0x00 701D
1
LPMCR0
0x00 701E
1
Low-Power Mode Control Register 0
LPMCR1
0x00 701F
1
Low-Power Mode Control Register 1
Reserved
0x00 7020
1
PLLCR
0x00 7021
1
PLL Control Register(2)
SCSR
0x00 7022
1
System Control and Status Register
WDCNTR
0x00 7023
1
Watchdog Counter Register
Reserved
0x00 7024
1
WDKEY
0x00 7025
1
Watchdog Reset Key Register
Reserved
0x00 7026 – 0x00 7028
3
WDCR
0x00 7029
1
Watchdog Control Register
Reserved
0x00 702A – 0x00 702F
6
(1)
All of the above registers can only be accessed by executing the EALLOW instruction.
(2)
The PLL control register (PLLCR) is reset to a known state by the XRS signal only. Emulation reset (through Code Composer Studio)
will not reset PLLCR.
Copyright © 2001–2012, Texas Instruments Incorporated
Functional Overview
49
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Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812



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