STTS2004 datasheet(8/58 Pages) STMICROELECTRONICS

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Serial communications

STTS2004

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Serial communications

The STTS2004 has a simple 2-wire I2C-compatible digital serial interface which allows the

user to access both the 4 Kb serial EEPROM and the data in the temperature register at any

time. It communicates via the serial interface with a master controller which operates at

speeds of up to 1 MHz. It also gives the user easy access to all of the STTS2004 registers in

order to customize device operation.

The device behaves as a slave device in the I2C protocol, with all operations synchronized

by the serial clock. Read and write operations are initiated by a START condition, generated

by the bus master. The START condition is followed by a device select code and R/W bit (as

described in Table 2 on page 10), terminated by an acknowledge bit.

The STTS2004 device is selected when decoding the correct device select byte. The device

select byte is comprised of the 4-bit Device Type Identifier (DTI) and the 3-bit select

address.

The SPD and TS portions of the STTS2004 device are designed to operate in parallel.

Accesses to each portion of the device may be interleaved as long as the command

protocol is followed.

When writing data to the memory, the STTS2004 inserts an acknowledge bit during the 9th

clock cycle, following the bus master's 8-bit transmission. When data is read by the bus

master, the bus master acknowledges the receipt of the data byte in the same way. Data

transfers are terminated by a bus master generated STOP condition after an ACK for

WRITE, and after a No ACK for READ.

The TS portion of the STTS2004 device uses a pointer register to access all registers in the

device. Additionally, all data transfers to and from this section of the device are performed

as block read/write operations. The data is transmitted/received as 2 bytes, Most Significant

Byte (MSB) first, and terminated with a No ACK and STOP after the Least Significant Byte

(LSB). Data and address information is transmitted and received Most Significant Bit first.

Note:

Clock stretching is not supported by the device.

Violations of the command protocol result in unpredictable operation.

2.1

Device type identifier (DTI) code

The JEDEC temperature sensor and EEPROM each have their own unique I2C address,

which ensures that there are no compatibility or data translation issues. This is due to the

fact that each of the devices have their own 4-bit DTI code, while the remaining three bits

are configurable. This enables the EEPROM and thermal sensors to provide their own

individual data via their unique addresses and still not interfere with each other’s operation

in any way.

The TS registers of the STTS2004 are accessed using a DTI of (0011).

A0, A1, and A2 inputs are directly combined with the DTI and the SPD page address bit to

qualify I2C addresses. Each of the address pins (A0, A1, A2) is tied to VDD or VSS for the

Logical Serial Address (LSA) which is equal to the code on the address pins (refer to

Table 1).

STTS2004 数据表(PDF) 8 Page - STMicroelectronics

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