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STTS2004

SPD EEPROM operation

5.1

4 Kb SPD EEPROM operation

The STTS2004 includes a 4-Kbit serial EEPROM organized as two pages of 256 bytes

each, or 512 bytes of total memory. Each page is composed of two 128-byte blocks. The

devices are able to selectively lock the data in any or all of the four 128-byte blocks.

The SPD is a 512-byte EEPROM device designed to operate the two-wire bus at a

maximum of 1 MHz transfer rate, in the 2.2 V - 3.6 V voltage range.

The SPD in the STTS2004 is protocol-compatible with the previous operation in the

STTS2002. The page selection method allows commands used with the STTS2002 to be

applied to the lower or upper pages of the EEPROM.

Individually locking a 128-byte block may be accomplished using a software write protection

mechanism in conjunction with a high input voltage VHV on input A0. By sending the device

a specific SMBus sequence, each block may be protected from writes until the write

protection is electrically reversed using a separate I2C sequence which also requires VHV

on input A0. The write protection for all four blocks is cleared simultaneously, and may be

re-asserted after being cleared.

5.2

Internal device reset - SPD EEPROM

In order to prevent inadvertent Write operations during power-up, a Power-On Reset (POR)

circuit is included.

At power-up (phase during which VDD is lower than VDDmin but increases continuously), the

device will not respond to any instruction until VDD has reached the Power-On Reset

threshold voltage (this threshold is lower than the minimum VDD operating voltage defined in

Table 29: Operating and AC measurement conditions). Once VDD has passed the POR

threshold, the device is reset.

Prior to selecting the memory and issuing instructions, a valid and stable VDD voltage must

be applied. This voltage must remain stable and valid until the end of the transmission of the

instruction and, for a Write instruction, until the completion of the internal write cycle (tW).

At power-down (phase during which VDD decreases continuously), as soon as VDD drops

from the normal operating voltage below the Power-On Reset threshold voltage, the device

stops responding to any instruction sent to it.

5.3

Memory addressing

To start communication between the bus master and the slave device, the bus master must

initiate a Start condition. Following this, the bus master sends the device select code, shown

in Table 2 (on serial data (SDA), most significant bit first).

The device select code consists of a 4-bit device type identifier, and a 3-bit slave address

(A2, A1, A0). To address the memory array, the 4-bit device type identifier is 1010b; to

access the write-protection settings, it is 0110b.

Up to eight STTS2004 SPD devices can be connected on a single I2C bus. Each one is

given a unique 3-bit code on the slave address (A0, A1, A2) inputs. When the device select

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