STTS2004 datasheet(35/58 Pages) STMICROELECTRONICS

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STTS2004

SPD EEPROM operation

Figure 12. Setting the write protection

5.4.2

RPSn: read protection status

The controller issues an RPSn command specifying which block to report upon. If the

software write protection has not been set, the device replies to the data byte with an Ack. If

it has been set, the device replies to the data byte with a NoAck.

5.4.3

SPAn: set SPD page address

The controller issues an SPAn command to select the lower 256 bytes (SPA0) or upper 256

bytes (SPA1). After a cold or warm power-on reset, the SPD page address is always 0,

selecting the lower 256 bytes.

5.4.4

RPA: read SPD page address

The controller issues an RPA command to determine if the currently selected SPD page is 0

(device returns Ack) or 1 (device returns NoAck).

5.5

Write operations

Following a Start condition, the bus master sends a device select code with the RW bit reset

to 0. The device acknowledges this, as shown in Figure 13, and waits for an address byte.

The device responds to the address byte with an acknowledge bit, and then waits for the

data byte.

When the bus master generates a Stop condition immediately after a data byte Ack bit (in

the “10th bit” time slot), either at the end of a Byte write or a Page write, the internal memory

Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal

Write cycle.

During the internal Write cycle, Serial Data (SDA) and Serial Clock (SCL) are ignored, and

the device does not respond to any requests.

SDA LINE

AI01935b

ACK

WORD

ADDRESS

VALUE

(DON'T CARE)

ACK

DATA

VALUE

(DON'T CARE)

ACK

CONTROL

BYTE

BUS ACTIVITY

MASTER

BUS ACTIVITY

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